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Voltage-Timing Signoff for Next Generation Ultra Low Voltage Designs

June 4, 2020 @ 11:30 AM - 12:30 PM

June 4, 2020

11:30 AM (IST)


Today’s advanced 16/7/5nm/3nm SoCs are faced with increased variation effects as they push for lower power. While the sizes of the transistors continue to shrink following Moore’s Law, the threshold voltages fail to continue to scale. Traditionally, dynamic voltage drop (DvD) signoff and timing signoff are done independently with margins/guard-banding based on historical/empirical experience. As we move to advanced SoCs, this approach can lead to chip failures. Ansys provides comprehensive workflows with foundry-certified accuracy for multiphysics simulations across power integrity and its impact on timing critical paths.

Join us for this webinar for a detailed analysis of Ansys’ multiphysics reliability signoff solution for next-generation, ultra-low voltage SoCs.

  • Learn how Ansys SeaScape and Ansys FX technologies combine to build a comprehensive voltage-timing solution that meets industry needs.
  • Discover how this Ansys workflow can accurately model dynamic voltage drop impact on timing and enable chip designers to quickly identify the important set of violations that they need to fix, prior to signoff.

Voltage-Timing Signoff for Next Generation Ultra Low Voltage Designs

Voltage-Timing Signoff for Next Generation Ultra Low Voltage DesignsVoltage-Timing Signoff for Next Generation Ultra Low Voltage DesignsSpeaker Bio

Vinayakam Subramanian joined Ansys in 2006 and is currently working as director of applications engineering, based out of Bengaluru. He loves to solve multiphysics challenges that require combining technologies across various domains. He is responsible for product management of voltage-timing simulation solutions for advanced chip designs.

Who Should Attend

  • IC design engineers
  • VLSI flows and EMIR/STA methodology engineers/managers
  • IC physical implementation/backend engineers/managers
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June 4, 2020
11:30 AM - 12:30 PM
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