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Questa Formal-Based Apps / Questa Formal Property Checking – What’s New in Functional Verification from Mentor: Session 4
June 4, 2020 @ 4:00 PM - 5:00 PM
This is the fourth of a 5-part series on “What’s New in Functional Verification from Mentor.” Each session will be presented twice at the times shown above consisting of two half-hour presentations, with Q&A. Please register for the time that is more convenient for you.
Improving Quality and Time-to-Market with Formal: Part 1, Automated Formal-based Apps
Many high-value verification tasks such as dynamic connectivity verification, register policy verification, or confirming the integrity of critical signal paths and registers – require weeks or months of testbench development and execution, and still do not uncover all the unexpected corner cases. In contrast, formal-based verification can exhaustively verify these challenges via applications – “apps” – that are automated to the point where they effectively eliminate the need to know about the inner workings of formal analysis, yet deliver the exhaustive results needed. Questa Formal provides a powerful set of automated apps that can be applied from early in the design phase throughout the verification process to identify hard-to-find corner cases early in the verification process where they are easier and cheaper to fix. In this web seminar we will show how formal apps can help you address the following high-value verification challenges.
What You Will Learn:
- Finding deep bugs in complex logic and avoiding deadlocks (long before a UVM testbench is available!)
- Accelerating code coverage closure via dead code analysis
- Uncovering register policy corner cases
- Verifying the correctness of all SoC and pad ring direct, conditional, and sequential connectivity
- Finding unintended (or maliciously added) backdoors or “sneak paths” to secure/safety critical storage
- Root-cause analysis of erratic failures from ‘X’ propagation due to low power or post-reset bring-up, or X-optimism
- Validating low power clock gating logic, late ECOs or bug fixes, or fault/SEU mitigation logic
Improving Quality and Time-to-Market with Formal: Part 2, Direct Formal Property Checking
Even well-written constrained-random testbenches cannot traverse every part of a design’s state space. The truth is that simulation-based verification is fundamentally incomplete for even small DUTs. Additionally, it can take many weeks before a simulation testbench is created, providing a window of opportunity for complex bugs to be written into the IP. Consequently, whether the given bug is due to an out-of-date or misunderstood spec, or is a fundamental design flaw, the longer it goes undetected, the more expensive it is to find, fix, and thoroughly validate the repair both fixes the bug and doesn’t create unwanted side-effects itself. In this webinar we will show how formal property checking enables high-value verification long before other methods are available, exhaustively discovering any design errors that can occur (and without needing specific stimulus!)
What You Will Learn:
- How formal analysis works, and how it provides exhaustive results valid for all inputs and all time
- How you can create an effective “formal testbench” with very basic, easy-to-write properties
- An introduction to popular formal verification methodologies: bug hunting, completely proving the correctness of critical DUT functions, and proving the absence of deadlock
Mark EslingerMr. Eslinger has over 20 years of experience in chip design & verification, pre/post sales support, and technical marketing. As a technical marketing specialist in the Design Verification Technology Division of Mentor Graphics Mr Eslinger has a special focus on assertion-based methods and formal verification. In this role he works with customers worldwide to help them adopting advanced methodologies. Prior to Mentor Mr. Eslinger has held positions in the engineering and technical marketing organizations in the semiconductor, systems and EDA industry, including Lockheed, Synopsys, Abstract, Sente/Sequence, Averant, and AccelChip. Mr Eslinger holds a MSEE from Santa Clara University.
Joe HupceyJoe Hupcey III is a part of the Mentor’s Product Management team for Design & Verification Technologies; based in Mentor’s office in Silicon Valley, CA. He is responsible for the Questa Formal product line of automate applications and advanced property checking. Prior to joining Mentor, Joe has held product management and marketing roles in several Electronic Design Automation (EDA) companies, for products that covered multiple aspects of hardware and software functional verification. Before transitioning into marketing, Joe worked as an electrical engineer in FPGA design, EDA tools for FPGAs and ASICs, and ASIC verification. Joe’s educational background includes BSEE, MSEE, and MBA degrees from Cornell University in Ithaca, NY.
- Questa® AutoCheck
- Questa® Connectivity Check
- Questa® CoverCheck
- Questa® Formal Assertion Library
- Questa® Post Silicon Debug
- Questa® PropCheck
- Questa® Register Check
- Questa® Secure Check
- Questa® X-Check
Who Should Attend
Design and Verification Engineers and Managers