Loading Events

« All Events

  • This event has passed.

SemIsrael Tech Webinar

May 2, 2023 @ 2:00 PM - 5:00 PM


SemIsrael, May 2, 2023

Webinar Agenda

Shine Chung web.jpg

Shine Chung


Attopsemi Technology

14:00 – 14:30

I-fuse® OTP, Metal fuse, ultra Low voltage OTP, FinFET technology, Automotive

Revolutionary Metal I-fuse® OTP in FinFET Tech

In this session, we will share the core competence of I-fuse® OTP and the revolution of Metal I-fuse® in FinFET technology, which proves the metal interconnect can be an ideal material for electro-migration as processes migrate, enabling the program voltage and current to be scaled as fabrication processes advance. Also, we will share some silicon data and comparison between other OTPs technology, expecting to offer valuable insights into this field.


Shine Chung graduated from Harvard University in the early 1980s. He started his career as an SRAM technologist and designer at AMD. He joined VLSI Design Associate as an ASIC circuit and logic designer in custom design projects later. Then he worked for HP Labs in the Super Workstation project since 1988. The RISC architecture he helped to define was transferred to Intel in 1994 as the Merced architecture and the corner stone of Itanium chips. After HP, he worked for Digital on StrongARM 1500, AMD on K5, and some startups on flash memory devices and designs. In 1999, he co-founded Audia Technologies, a hearing-aid IC and device company.

In 2003, he returned to Taiwan and worked for TSMC as a Director in Design Service Division to develop various IPs such as SRAM, embed-DRAM, electrical fuse, and emerging memories. He single-handedly built up the TSMC’s electrical fuse program from 0.13um to 90nm. He published two highly acclaimed papers on electrical fuse in VLSI Circuit Symposium 2007 and 2009, respectively. He was a two-time TSMC Corporate Innovation Award recipient in 2007 and 2008 for developing electrical fuse and logic bipolar device, respectively. He retired from TSMC in the early 2010 and founded Attopsemi Technology half a year later.

Umesh web.jpg

Umesh Sisodia



14:30 – 15:00

SystemC, Virtual Prototypes, System Level Design

Transforming Semiconductor Design Using SystemC Based Shift-left ESL Methodologies

This webinar will cover the SystemC based shift-left ESL methodologies, which are becoming integral part of the design flow for designing advanced System on Chips and Electronics systems of today.

These ESL methodologies do not replace the traditional RTL-GDS flow, but rather co-exist with existing flow and augment it to perform various advanced activities which are not feasible with traditional flow. It enables Pre-Silicon firmware development, Architecture exploration to optimize power & performance early in the cycle at system level, High-Level Synthesis (HLS), SoC Level simulation, System level simulation, Hardware-Software co-design, and co-verification.


Umesh Sisodia is the Founder & CEO of CircuitSutra Technologies, a company focusing on SystemC based shift-left ESL methodologies. He has more than 25 years of experience in the Semiconductor industry and worked with Cadence & Semiconductor complex Ltd before starting CircuitSutra in 2005.  

Umesh started India SystemC Conference in 2012, which was later merged with DVCon India in 2014 & Umesh was the first general chair of DVCon India in 2014. He was awarded by Accellera Systems Initiative for his significant contribution in driving Accellera standards in the Indian ecosystem.

Roger Espasa web.jpg

Roger Espasa

CEO & Founder


15:00 – 15:30

RISC-V, Out-of-Order IP Core, Vector Unit

RISC-V OOO IP Core and Vector Unit

In this contribution we will describe Semidynamic’s RISC-V IP comprising its advanced family of out-of-order cores (code named Atrevido) and the companion out-of-order vector unit, fully compliant to the RISC-V 1.0 specification. The core and vector unit contain the Gazzillion(tm) misses technology, which make them ideal for environments with high memory latency and/or high bandwidth demands, such as CXL memory systems or HBM memory systems.


Roger Espasa is the founder and CEO of Semidynamics, an IP supplier of two RISC-V cores, Avispado (in-order) and Atrevido (out-of-order) supporting the RISC-V vector extension and Gazzillion TM misses, both targeted at HPC and Machine Learning. In addition, Semidynamics architected and designed the Esperanto Technologies’ 1024+ core machine-learning 7nm SoC. Prior to Semidynamics, Roger was at Broadcom working on an ARMV8 wide out-of-order core. (2014-2016). Previously, Roger worked at Intel (2002-2014) developing a vector extension for the x86 ISA, initially deployed in XeonPhi (Larrabee) which then became AVX-512. Roger also led the texture sampling unit for Larrabee. Roger then worked on Knight’s Landing (14nm) and led the core for Knights Hill (10nm). Between 1999 and 2001 Roger worked for the Alpha Microprocessor Group on a vector extension to the Alpha architecture known as Tarantula. Roger got his PhD from UPC in 1997, has published over 40 peer-reviewed papers on Vector Architectures, Graphics/3D Architecture, Binary translation and optimization, Branch Prediction, and Media ISA Extensions and holds 9 patents with 41 international filings.

Siddharth Ravikumar.PNG

Siddharth Ravikumar

Technical Product Manager, Solido IP Validation

Siemens EDA

15:30 – 16:00

IP, QA, Validation, analog, digital, mixed-signal, Solido

IP QA Best Practices

As modern System-on-Chips (SoCs) become larger and more complex, design IPs have become essential building blocks. Design IPs allow for modularization and re-use of design components, which is crucial for managing the increasing scale and complexity of SoCs. However, IP data library can be vast and contain multiple views and formats, leading to potential inconsistencies that may be difficult to identify.

A robust QA framework for design IPs which can detect inconsistencies early in the flow is a crucial component for successful silicon production.

Implementing a proper QA methodology can ensure that critical metrics such as consistency, accuracy, and completeness are met, leading to better silicon quality and shorter production schedules.

A robust IP QA framework should possess the following capabilities: 
sign- and technology-agnostic IP QA: The framework should focus on identifying issues early in the flow, regardless of the underlying design methodology or technology node being used. 

Comprehensive validation coverage: The validation methodology should cover a wide range of checks to ensure thorough verification. 

Adaptability to changing specifications: Performance and specifications may change at each revision made to the design IP. Therefore, the QA methodology must have the ability adapt to these changes.

Flexibility for adding functionality: To support a wide range of use cases, the QA methodology should be extensible, and allow for the addition of custom functionality to complement existing built-in checks. 

In this webinar, we will explore the different challenges and risks in IP QA and discuss how a robust IP QA tool can mitigate them. We will delve into the various checks, such as syntax checks, in-view and cross-view consistency checks, timing arc checks, layout comparisons (e.g., LEF versus GDS), and others, that can identify potential issues early in the design flow and improve the overall quality of design IP.


Siddharth Ravikumar is a seasoned professional with over 11 years of experience in the semiconductor industry. He has a background in front-end design and verification, as well as test engineering. He currently serves as a Technical Product Manager for Solido IP Validation at Siemens EDA, where he brings his expertise to develop and launch innovative products. Siddharth holds a Master’s degree in Electrical Engineering from Santa Clara University

Seaholm Michael web.jpg

Michael Seaholm

Product Manager for Performance Oscilloscopes and Margin Testing

Tektronix Inc.

16:00 – 16:30

PCIe Gen 3 and Gen 4 testing, Tx/Rx, eye diagrams

New disruptive Solution to get Insights into PCIe Validation and Link Health

As successive generations of PCI Express (PCIe) continue to double the data rates roughly every 3 years, the time and complexity of testing has risen exponentially. And while test equipment like oscilloscopes and bit error rate testers (BERTs) have met the bandwidth requirements for this testing, less focus has been on improving test times and reducing test complexity as these data rates rise.

In a world where time to insight is becoming increasingly critical, Tektronix has recognized the need for a new category of test equipment that is focused on optimizing test time and improving ease of use. Join us for this session on the latest product from Tektronix, the TMT4 Margin Tester, where we will provide a brief overview of the instrument, and discuss some examples of how this new product can improve your PCIe Gen 3 and Gen 4 testing.


Michael Seaholm is a Product Manager for Performance Oscilloscopes and Margin Testing at Tektronix Inc. He has spent five years as a Product Manager in the Test and Measurement industry, including three years at Fluke Corporation and two years at Tektronix Inc. Michael has a BSEE in Electrical Engineering from Montana State University and has spent his career in Product Management focused on bringing new innovation to test and measurement through consistent engagement with customers

Larry Lapides

VP Worldwide Sales

Imperas Software

Larry_Lapides_Formal web.jpg
16:30 – 17:00

RISC-V Verification & Software Development

Advanced RISC-V Processor Verification Methodology

The open standard of RISC-V offers developers new freedoms to explore new design flexibilities and enable innovations with optimized processors. As a design moves from concept to implementation new resources are appearing to help with standards for testbenches, verification IP reuse and coverage analysis. RISC-V offers every SoC team the possibility to design an optimized processor, but this also implies the SoC design verification teams will need to address the challenge and complexity of processor verification.

This presentation outlines methodologies that assist in both the efficiency and support for the growing community of RISC-V adopters.  The focus is on more complex RISC-V processors, and methodologies that account for asynchronous events:  interrupts and debug operations, plus hardware configurations including multi-issue and Out-Of-Order pipelines, multi-hart processors, vector extensions and custom instructions.


Larry is currently VP Worldwide Sales at Imperas Software Ltd., and previously ran worldwide sales at EDA companies including Calypto and Verisity Design.  Larry has about 30 years in software tools and EDA, plus time spent in infrared systems engineering.  Larry holds a BA in Physics from the University of California Berkeley, a MS in Applied and Engineering Physics from Cornell University and a MBA from Clark University where he was an Entrepreneur-in-Residence during Fall 2006, when he developed and taught the course on Entrepreneurial Sales. 


Share this post via:


May 2, 2023
2:00 PM - 5:00 PM
Event Tags:
, ,