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Porting Vivado HLS Designs to Catapult HLS Platform

November 3, 2020

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Register For This Web Seminar

Online – Nov 3, 2020
10:00 AM – 11:00 AM US/Pacific
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High-Level Synthesis (HLS) offers significant benefits when developing algorithms and intellectual property (IP) blocks for implementation in digital logic solutions such as Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASICs). FPGA vendors offer HLS tools and using those increases flexibility and productivity over traditional hardware description language (HDL) flows. But employing FPGA vendor-specific tools can limit the portability of the design outside of their ecosystem. To regain the flexibility of targeting a design to another technology requires porting the design from the vendor’s HLS environment into an HLS environment that supports any ASIC or FPGA technology.

What You Will Learn

  • How to port an existing HLS design developed within the Xilinx® Vivado® HLS environment into Mentor’s Catapult® HLS Platform
  • The differences in libraries and data structures
  • How to port optimizations from Vivado to Catapult

Who Should Attend

  • Designers who are interested in creating a portable solution of ASIC implementation
  • Engineering Managers who want to know how to leverage existing code bases in new technologies
  • HLS/RTL designers who are interested in learning about Catapult HLS
  • Algorithm Developers
  • System Architects
Adam Taylor

Adam TaylorAdam Taylor is an expert in the design and development of embedded systems and FPGA’s for several end applications. Throughout his career, Adam has used FPGA’s to implement a wide variety of solutions from RADAR to safety-critical control systems (SIL4) and satellite systems. He also had interesting stops in image processing and cryptography along the way. Adam has held executive positions, leading large developments for several major multinational companies. For many years Adam held significant roles in the space industry he was a Design Authority at Astrium Satellites Payload processing group for 6 years and for three years he was the Chief Engineer of a Space Imaging company, being responsible for several game-changing projects. FPGAs are Adam‘s first love, he is the author of numerous articles and papers on electronic design and FPGA design including over 330 blogs and 25 million-plus views on how to use the Zynq and Zynq MPSoC for Xilinx. Adam is a Chartered Engineer, Fellow of the Institute of Engineering and Technology, Visiting Professor of Embedded Systems at the University of Lincoln, and Arm Innovator, he is also the owner of the engineering and consultancy company Adiuvo Engineering and Training.

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