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Optimizing Hardware Layout Designs

June 24 @ 11:00 AM - 12:00 PM

June 24, 2020

11 AM EDT / 3 PM GMT

Venue:
Online

This webinar showcases how a leading-edge hardware design process bridges the challenging gaps that occur between analysis and layout design. We will examine typical discrepancies that range from translating geometry between layout and simulation environments to communicating changes from the analysis back to the layout. Further, we’ll spotlight various mechanisms and data types that will optimize your information exchange and ensure your process accuracy.

  • Discover how to significantly enhance your hardware layout designs with Ansys’ electronics workflow.
  • Receive expert tips for overcoming the typical challenges that occur between analysis and layout design.
  • Learn how to leverage the key mechanisms and data types that will enhance your information exchange and ensure your process accuracy.

Who Should Attend

Hardware simulation engineers (electrical and mechanical), PCB and IC package designers, hardware simulation engineering managers.

Speakers

Lance Wang, Solutions Architect, Zuken

Jim Delap, Lead Electronics Products Manager, Ansys