DVClub Europe: Latest VHDL Verification Techniques

DVClub Europe: Latest VHDL Verification Techniques

This DVClub focuses on the latest verification techniques in VHDL including UVVM and OSVVM

Agenda (GMT)

13:00 Welcome and Introduction – Mike Bartley, Tessolve

13:00 Espen Tallaksen, EmLogic – Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage)

13:30 Jim Lewis, SynthWorks

14:00 Close

Additional Information

For additional information please visit the Tessolve DVClub Europe webpage for this event.

Sponsors

DVClub Europe is made possible through the generous support of our sponsors: Agnisys, Cadence, Breker Verification System, Synopsys

Tessolve reserves the right to cancel registration at its discretion.

REGISTER HERE