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Design adaptive eFPGA IP: the benefits of programmable logic without pain

September 29, 2020 @ 10:00 AM - 11:00 AM

Despite the current health crisis, we are living through an unprecedent era of innovation – and this is not going to slow down as well captured by the law of accelerating returns. Disruptive and rapid change is now the new constant. The rate of architectural and algorithmic innovation is outpacing traditional chip development cycles.

This is not only true for AI, but also for communication protocols, encryption, compression, interconnect fabrics and cybersecurity. The old world order of computing has now fractured beyond recognition.

Now is the time to design chips to be at least partially reconfigurable to adapt to emerging needs. Embedded programmable logic, in the form of embedded FPGA (eFPGA) IP, is now making its way in SoCs as an answer to these challenges, with multiple design wins announced by the main eFPGA IP providers. In this webinar, we will explain what makes an eFPGA different to a FPGA but also to embedded CPUs/GPUs – and in which cases an eFPGA IP is the way to go. We will then explain what is a design adaptive eFPGA IP and why this adaptiveness is so important when it comes to integrating an eFPGA IP.

SPEAKER: YOAN DUPRET, MANAGING DIRECTOR, MENTA Before joining Menta in 2016, Yoan worked more than 15 years in the semiconductor industry at various management and technical positions in companies such as DelfMEMS, Samsung, CSR, Infineon and Altis Semiconductor. In addition to his embedded FPGA expertise, Yoan worked on topics as various as RF MEMS design, EDA, PDK, MOS and passives RF modeling, statistical simulation and manufacturing yield modeling. Yoan holds a PhD from Supelec and a master degree from ESEO, France.

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September 29, 2020
10:00 AM - 11:00 AM