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Conquer SI/PI Challenges and Reduce Time to Signoff for PCIe 6.0
May 19 @ 10:00 AM - 11:00 AM
The Peripheral Component Interconnect Express (PCIe®) high-speed interface has become the standard for computer expansion cards due to its high bandwidth combined with manageable component costs. However, the latest PCIe 6.0 release raises new challenges for design engineers, as the popular interface standard moves to pulse-amplitude modulation-4 (PAM-4) signaling for the first time. This webinar will help you learn how a full Cadence® design and analysis flow can reduce your time to signoff for PCIe 6.0 devices by up to two months. It will present solutions for the signal integrity (SI) and power integrity (PI) challenges associated with the new PCIe 6.0 standard, along with early what-if analysis scenarios using system-level exploration technology that guides design teams toward optimized solutions. This webinar will also discuss in-design analysis, which enables simulation early in the design process, and often throughout the design cycle, to provide unique insights and guide engineers to first-pass success.
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