Cadence TECHTALK: Low-Power Verification using Xcelium Simulation

Time: 09:00 BST / 10:00 CEST / 11:00 EEST and Israel / 13:30 IST

The Cadence low-power solution considers power at every step of the design flow, from architecture to functional verification, analysis, implementation, and signoff. In this webinar, the focus will be on the functional verification of the RTL with the power intent defined in the IEEE 1801, aka UPF, format.

Low-power verification adds another layer of complexity to functional verification. Power-related issues often appear late in the verification cycle, can be difficult to fix, and may impact project schedules.

Low-power verification using Xcelium simulation enables design verification teams to catch low-power issues very early in verification cycle at RTL phase with best-in-class performance and providing complete low-power coverage. The Xcelium platform can automate low-power checkers and assertions using UPF Information Model, Query commands, and custom built-in functions. Xcelium simulation has advanced technology to differentiate the source of ‘X’ coming from LP versus functional ‘X’. Mixed-signal designs with real power supplies and custom resolution functions work seamlessly with UPF. The Verisium Debug App has advanced capabilities just to debug the complex low-power simulation.

This webinar will cover, not only the technologies mentioned above but many other new capabilities and the best practices using Xcelium simulation.