Advanced Debugging Workshop

This 4-hour workshop is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, and embedded systems using the Vivado® Design Suite. The features and capabilities of the Vivado Integrated Logic Analyzer are covered in lectures and demonstrations, along with general debugging concepts, tools and techniques. Special topics include helping guide attendees through the differences of using ISE® Design Suite based ChipScope™ in Vivado® for migrating to 7 Series devices and onward.

Additionally, this workshop will cover common gotchas and roadblocks engineers commonly face when both implementing FPGA designs and bringing up PCBs for the first time. The demonstrations utilizing actual Xilinx ZCU104 Evaluation Boards provide attendees with experience designing, expanding and modifying an embedded system, including techniques for triggering on boot and hardware-software co-debugging.

This workshop is based on BLT’s 1-day class Advanced Debug Techniques for Hardware Engineers.

COST:

AMD Xilinx is sponsoring this workshop, with no cost to students. Limited seats available.

WHO SHOULD ATTEND:

Hardware engineers, system architects, and anyone who wants to learn how to debug challenging issues encountered while developing with FPGAs, SoCs, ACAPs, and PCBs.

SKILLS GAINED

After completing this comprehensive training, you will know how to:

• Identify synchronous design techniques
• Use the Vivado™ logic analyzer and debug flows to debug a design
• Debugging a design with multiple clock domains with the help of multiple debug cores using the Vivado™ logic analyzer
• Debugging a design at the device startup phase to debug issues related to startup events, such as MMCM lock and design coming out of reset