Integration Methodology of High-End SerDes IP into FPGAs

Over the last couple of decades, the electronics communications industry has been a significant driver behind the growth of the FPGA market and continues on. A major reason behind this is the many different high-speed interfaces built into FPGAs to support a variety of communications standards/protocols. The underlying input-output PHY technology involved in implementing these standards is the serializer-deserializer (SerDes) technology. FPGA as a technology is complex and challenging to begin with, even before high-speed interfaces are taken into account. And SerDes PHY designs are complex and challenging in their own right. When these two are brought together, the implementation gets trickier, which is generally why there is a lag in incorporating the most advanced SerDes designs into FPGAs. But what if the status quo can be changed? This was the objective behind a collaborative effort between Alphawave IP and Achronix, the results of which were presented at the TSMC OIP Forum in October.

Challenges in Integrating High-End SerDes into FPGAs

Interdependencies between the SerDes and the FPGA fabric may lead to floorplanning challenges for the integrated chip. In addition to the layout challenges, even minor differences in metal stack choices between the fabric and the SerDes may adversely impact the power, performance and area (PPA) of either of these components.

FPGAs have to support a large number of line rates and protocols and protocol variants with diverse electrical channel requirements. The line rates range from 1Gbps to 112Gbps using NRZ or PAM4 signaling schemes to deliver the speed performance. This combinatorial requirement places a heavy burden on the modeling used for simulations. Each line rate/protocol combination needs to be validated pre-silicon and post-silicon based on highly accurate models.

Requirements for Successful Integration

Whether it is the SerDes or the FPGA fabric, architectural enhancements are made which will impact the SerDes integration with the FPGA fabric. To avoid surprises at integration time, architectures need to be discussed early on and agreed upon so proper sim models can be developed for validating. An overly optimistic model would force a radical change in the architecture and an pessimistic model would deliver a PPA uncompetitive solution. Neither of these two situations are desirable.

A close collaboration between the SerDes IP vendor and the FPGA integrator is required early on for developing accurate models. The close partnering is also needed for ensuring optimal floorplanning, power planning, bump map planning, timing, etc.

Scope of Alphawave IP and Achronix Collaboration

Achronix’s high-end FPGAs support multi-standard protocols such as 1GbE through 400GbE, PCIe Gen5, etc., including custom protocols to support non-standard speeds such as 82Gbps (for example). The SerDes 112 Gbps uses a different architecture compared to the 56Gbps SerDes and uses the PAM4 signaling scheme. The design uses a digital ADC and is a built around a DSP-based architecture.

The goal of the collaborative effort was to achieve successful integration of Alphawave IP’s AlphaCORE100 multi-standard SerDes with Achronix’s Speedster7t FPGA fabric.

Test Chip

A Test chip was built to validate the early sim models. The Test chip was implemented in TSMC’s N7 process and included four data channels, full AFE, digital PLLs and DLLs, BIST and additional test circuity for characterization.

Successful Results

As presented in the plots below, the simulation results based on the early models developed through the collaborative efforts correlated very well with Test chip measurements in the lab. The high accuracy models enabled Achronix to produce first-time-right Speedster7t FPGAs with Alphawave IP’s AlphaCore100 SerDes IP to support PCIe Gen5x16 and Gen5x8 as well as 400GbE.

The results of full simulation also correlated well with BER measurements from the lab for a wide range of channel loss conditions.

For more details, please connect with Achronix and Alphawave IP.

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