SA-EDI Workshop: “A Practical Guide to SA-EDI Methodology”

SA-EDI Workshop: “A Practical Guide to SA-EDI Methodology”
by Admin on 02-20-2024 at 4:16 pm

Accellera at DVCon US 2024

Authors:

  • Jean-Philippe Martin, Intel
  • Mike Borza, Synopsys

Topic(s): Security

Keywords: security, asset, accellera, sa-edi, IEEE P3164, threat modeling

Abstract: This workshop will demonstrate how to identify assets in intellectual property (IP) in accordance with Accellera’s Security Annotation… Read More


Webinar: Efficient Design Methodology for 112G Interface Compliance

Webinar: Efficient Design Methodology for 112G Interface Compliance
by Admin on 02-07-2024 at 11:13 pm

As 112G+ data transfer becomes the new normal, companies risk schedule delays unless they improve the efficiency of their multi-board design methodology. An efficient design methodology looks at signal and power integrity early and often as the design progresses. In addition, with the precision required to meet 112G compliance,… Read More


Webinar: Efficient Design Methodology for 112G Interface Compliance

Webinar: Efficient Design Methodology for 112G Interface Compliance
by Admin on 12-26-2023 at 8:30 pm

Description

As 112G+ data transfer becomes the new normal, companies risk schedule delays unless they improve the efficiency of their multi-board design methodology. An efficient design methodology looks at signal and power integrity early and often as the design progresses. In addition, with the precision required to meet… Read More


DVCon: Sponsored Workshop: A Methodology for Power and Energy Efficient Systems Design

DVCon: Sponsored Workshop: A Methodology for Power and Energy Efficient Systems Design
by Admin on 01-25-2023 at 2:31 pm

Power is everywhere. Traditionally, power used to be a concern with mobile and handheld devices due to battery life considerations. But now, power as a concern is prevalent in all verticals of the industry, for example, data centers consume huge amounts of power due to million of data transactions happening per second. Processors… Read More


Integration Methodology of High-End SerDes IP into FPGAs

Integration Methodology of High-End SerDes IP into FPGAs
by Kalar Rajendiran on 11-29-2022 at 6:00 am

AlphaCORE100 Multi Standard SerDes

Over the last couple of decades, the electronics communications industry has been a significant driver behind the growth of the FPGA market and continues on. A major reason behind this is the many different high-speed interfaces built into FPGAs to support a variety of communications standards/protocols. The underlying input-output… Read More


A PI Engineer’s Guide to Up-Leveled Signoff Methodology

A PI Engineer’s Guide to Up-Leveled Signoff Methodology
by Admin on 08-16-2021 at 1:54 pm

August 26, 2021

Overview

Power integrity (PI) engineers have been running Cadence®Sigrity™ tools to perform DC, AC, and power-ripple analysis for decades.  Sigrity X technology is recognized by the industry as simply the best to ensure that sufficient, efficient, and stable power is delivered to the components in your design.  

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Heterogeneous Chiplets Design and Integration

Heterogeneous Chiplets Design and Integration
by Kalar Rajendiran on 05-28-2021 at 6:00 am

Transistor Cost per Billion 3nm Projection

Over the recent years, the volume and velocity of discussions relating to chiplets have intensified. A major reason for this is the projected market opportunity. According to research firm Omdia, chiplets driven market is expected to be $6B by 2024 from just $645M in 2018. That’s an impressive nine-fold projected increase over… Read More


An Informal Update

An Informal Update
by Bernard Murphy on 10-05-2017 at 7:00 am

I mentioned back in June that Synopsys had launched a blog on formal verification, intended to demystify the field and provide help in understanding key concepts. It’s been a few months, time to check in on some of their more recent posts.


First up, it feels like they are finding their groove. Relaxed style, useful topics but now with… Read More


Prototyping GPUs, Step by Step

Prototyping GPUs, Step by Step
by Bernard Murphy on 08-15-2017 at 7:00 am

FPGA-based prototyping has provided a major advance in verification and validation for complex hardware/software systems but even its most fervent proponents would admit that setup is not exactly push-button. It’s not uncommon to hear of weeks to setup a prototype or of the prototype finally being ready after you tape-out. … Read More