WP_Term Object
    [term_id] => 43
    [name] => Magwel
    [slug] => magwel
    [term_group] => 0
    [term_taxonomy_id] => 43
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 20
    [filter] => raw
    [cat_ID] => 43
    [category_count] => 20
    [category_description] => 
    [cat_name] => Magwel
    [category_nicename] => magwel
    [category_parent] => 157
    [is_post] => 1

Magwel’s Current Tools Take an Active Role in Power Transistor Design

Magwel’s Current Tools Take an Active Role in Power Transistor Design
by Tom Simon on 12-03-2015 at 7:00 am

It often seems that semiconductor industry coverage focuses on large digital markets like microprocessors or high frequency analog designs for RF applications. Yes, these are large markets, but power transistors like IBGT and VFETS make up a large and crucial sector. Not only do they make their way into discretes, but they are an important part of the mobile and IoT market where they are used for PMICs and a variety of high power and high voltage applications.

A power transistor is not a single junction but actually dozens or often thousands of parallel junctions operating in concert. Just as in digital circuits there is a premium on switching speed and coherence so that junctions are operating with the least resistance. Due to the large distributed nature of these devices, the parasitics from the metal and poly interconnect and gate and junction play a significant role in determining device performance. Engineers designing power transistors need to look at an extensive range of characteristics to fully model device behavior so they can optimize them.

Magwel is an EDA supplier that has made power transistor modeling one of its specialties. They offer a suite of tools known as PTM (Power Transistor Modeler) for addressing the needs of power transistor designers. Because I have been working with Magwel I have become much more familiar with these products.

One of the fundamental parameters of a power transistor is its drain-source resistance (Rdson). Magwel’s base PTM product predicts Rdson by combining linear or non-linear models for the junction when it is fully switched on with a detailed analysis of the metal and poly network connecting the source and drain terminals. This is a large network with many parallel paths, due to the large number of parallel active areas. To calculate this all the current paths are analyzed.

The user specifies the source and drain voltages or currents as fixed values or using excitation from a Voltage Controlled Voltage Source (VCVS) which is helpful for designing sense devices. The channel can be modeled linearly with a specified channel resistance or non-linearly to account for debiasing. PTM results include voltages, IR drop, resistance per layer and current densities, which are used to predict reliability information and to look for electro-migration violations.

PTM features a field viewer that shows voltage and current density overlaid on the layout. In addition to 2-D views, plots of the results from user selected 1-D cross-cuts can be generated. PTM also creates comprehensive reports in csv format for later analysis.

After Rdson, gate delay is one of the next most important factors determining device performance. PTM-GD uses a 64 bit mesh based solver to extract the distributed RC networks for the gate metal and poly interconnect up through the metal stack to the device terminals. To allow accurate and fast analysis PTM-GD uses distributed RC or distributed spice models to model the distributed nature of the gate network. SPICE is then used to compute the gate delay values.

So far we have been talking about steady state behavior, but modeling dynamic switching behavior provides an even better understanding of a power device. Magwel’s PTM-TR offers a view of the full transistor behavior over time. Using its visual feedback, designers can optimize switching performance to ensure faster and more uniform transitions across the device, minimizing power dissipation. This is especially useful for minimizing dead-time or shoot-through current in DC-to-DC converters.

PTM-TR produces a distributed model for the gate, drain and source networks. The active areas are segmented using SPICE derived table models so that the full switching behavior can be modeled in detail. At each time of interest during switching it is possible to see the voltages and currents across the device. This makes it possible to optimize the layout to provide more optimal switching minimizing dead-time, current crowding and shoot-through currents. For example, in the case of converters, it is possible to model high-side and low-side devices operating together to obtain a very accurate transient performance of the converter.

The final critical performance element is thermal behavior. High currents generate joule heating in the active areas and interconnect for the source and drain that in turn affect electrical properties of the device. Other external heat sources and sinks also play a factor in the thermal environment of the device. Using PTM-ET designers can fully define thermal sources and sinks in the package and even in the board. PTM-ET calculates thermal heating during operation by simultaneously solving the electrical and thermal equations for the circuit. Doing this fully considers the interdependency between thermal and electrical operation.

We all enjoy our mobile and battery powered devices, but without highly efficient power management circuits their battery life will disappoint, leaving us without their full benefits. Thus we find that optimal design for these circuits is paramount. Magwel’s Power Transistor Modeling suite offers a complete solution for ensuring optimal power transistor performance during all aspects of circuit design. For more information please visit the Magwel website at www.magwel.com.