Memory Controller IP, battle field where Cadence and Synopsys are really fighting face to face. Today let’s have a look at Cadence’s strategy.

I have shared with you last year some strategic information released by Cadence in April about their IP strategy, more specifically about the launch of the DDR4 Controller IP. And try to understand Cadence strategy about Interface IP in general (USB, PCIe, SATA, DDRn, HDMI, MIPI…) and how Cadence is positioned in respect with their closest and more successful competitor in this field, Synopsys.

When Cadence has acquired Denali for $315M, less than two year ago, one of the nuggets was the DDRn controller IP product line built by Denali during the last 10 years. Denali’ DDR controller IP was well known within the industry, doing pretty well with sales estimated to be slightly less than $10M in 2009 and $18M in 2011, but Denali is now part of Cadence. Their product was nice, but still based on a Soft PHY, making life more complicated for the designer having to integrate it. Synopsys DDR Controller IP (coming from the acquisition of MOSAID in 2007) was already based on a hard PHY, as well as Virage’ product (coming from the acquisition of INGOT in 2005). That’s why Denali had to build a partnership with MOSYS (in fact Prism Circuit before to be acquired in 2009) to offer a solution based on a hard PHY (from MOSYS) and their DDR3 Controller. This was before the acquisition of Denali by Cadence, we will see that Cadence rely now on a hard PHY based solution. In May 2010, date of the acquisition of Virage Logic by Synopsys, the DDR Controller IP market was already growing fast, and was very promising: (estimated) Y/Y growth for 2010 was 40%, as well as for 2011. In fact we now expect the DDRn IP market to have doubled between 2011 and 2009!

The reasons for growth are multiple, but the growth itself could seem to be a paradox in a market where the number of ASIC design start is declining. Here is the explanation: the proportion of SoC design start in respect of ASIC design start is growing faster, so the net count of ASIC integrating a processor (or Controller, DSP) core is growing. When you integrate a processor, you need to access an external memory (the cost of embedded DRAM being prohibitive) so you need t integrate a DDRn Controller. Considering the ever increasing memory Interface frequency, and the related difficulty to build a DDRn Controller in-house, the make vs buy question leads more frequently to select an external solution, or to buy an IP. This is why the forecast for the DDR Controller IP market, even the more conservative, shows a x3 multiplication between 2009 and 2013. And when we compare the DDR IP market with the other Interface IP market, we expect it to be the faster growing market, see figure:

With this history in mind, you better understand why it was important for Cadence to be the first to launch a DDR4 Controller IP. Proposing a hard PHY option is a way to catch up with Synopsys, who offer hard PHY systematically for the DDR IP product. The lack of such a hard PHY was a weakness of the Denali DDRn IP product line, this explain why Denali had built a partnership with Prism Circuit in April 2009 to offer a complete solution based on a (soft) Controller from Denali and a (hard) PHY from Prism Circuit. Ironically, both companies have been acquired in the meantime…

If we look at the IP market, at least at the Interface IP segments (USB, PCIe, SATA, HDMI, DDRn, MIPI…), we see that the positioning of Cadence is concentrating on the Memory Interface segments: DDRn and Nand Flash Controller (we will talk about it very shortly!). When Synopsys is active in all the above mentioned segments, with a dominant position (more than 50% market share) in USB, SATA, PCIe, DDRn and a decent (but unknown) position in HDMI and MIPI. This will certainly leave the door open for Synopsys to consolidate their dominant position, and build a product line of more than $250M on a $500M market (IPnest evaluation of the Interface IP market in 2015). To summarize, Mentor Graphics gave up in 2005 on the IP market, and the last announcement from Cadence means that they will attack 30% only of this market (the DDRn, PCIe and Nand Flash Controller IP) and give up on the remaining 70%, which will represent more than $300M in 2015. Nevertheless, the list of Cadence’ design-in in this area is quite impressive, including design-in made by Denali:

By Eric Estevefrom IPNEST – “Interface IP Survey 2004-2010 – Forecast 2011-2015” Table of Content available here