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Speeding SoC timing closure

Speeding SoC timing closure
by Paul McLellan on 01-12-2012 at 1:42 am

 As chips have become larger, one of the more challenging steps is full-chip signoff. Lots of other steps in the design process can work on just a part of the problem, but by definition full-chip signoff has to work on the full chip. But it is not just that chips have got larger, the number of corners that need to be validated has also exploded. And, of course, signoff is the last step before tapeout and so is on a critical part of the critical path under the most intense schedule pressure.

Over the last year or so Magma has introduced a suite of tools to address these issues. The first tool is the QCP extractor. You can’t have accurate timing without accurate parasitic data. The next tool is Tekton for delay calculation and static timing analysis. And thirdly there is Quartz DRC/LVS for physical verification.

These tools are multi-threaded and so scale to very large designs and can take advantage of compute farms. A further optimization is multi-mode, multi-corner analysis and extraction that allow a single server to concurrently analyze many scenarios and thus reduce the time and resources required. Magma’s place and route is now also built on top of these same basic extraction and analysis engines, thus removing correlation problems that can arise if the place and route system uses an approximation that the subsequent verification flags as incorrect.

There is a new webinar that explains how the sign-off technologies enhance the overall flow and are integrated together into a complete sign-off solution.


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