The Complexity of Block-Level Placement @ 56thDAC

The recent Design Automation Conference in Las Vegas was an indication of how the electronics industry is evolving.  In its formative years, DAC was focused on the fundamental algorithms emerging from academic research and industrial R&D, that enabled the continuation of the Moore’s Law complexity curve.  (Indeed, the most prestigious award at this year’s DAC recognized the scan-based Design for Test implementation that has become the de facto standard throughout digital semiconductor design.)  More recently, DAC added the “Design Track” and the “IP Track” sessions, to highlight the innovative methodologies that designers were using, leveraging the advances in EDA capabilities.

The evolution of electronic design applications was a prevalent theme at this year’s conference, with a multitude of sessions covering diverse topics:

• optimization of machine learning architectures for both data-center and edge inference engines (especially, resilience approaches to reduce the susceptibility to malicious attacks)
• opportunities for in-memory/near-memory processing on large datasets (a significant change to the traditional von Neumann architecture)
• advances in packaging technology for heterogeneous integration, especially for a “chiplet-based” design implementation

Nevertheless, the importance of ongoing innovations in fundamental EDA algorithms and products remains vital to the industry.  (The Best Paper award at the conference was presented to the authors of a unique approach to cell placement.)

At the conference, I had an opportunity to talk with Vinay Patwardhan, Product Management Director in the Digital & Signoff Group at Cadence.  We discussed the characteristics of current SoC designs for these new applications, and the demands they were placing on existing design implementation flows.  The insights (and customer data) that Vinay shared were very enlightening.

“Customers are pursuing extremely high cell count designs, enabled by advanced process nodes.  Good examples are cloud-scale ASICs.”, Vinay explained.  “The amount of memory integrated into these designs exceeds the logic and IP reuse functionality, and the trend is growing.”

In the figure below, the red bars represent the % SoC die area occupied by memory over time, the dark grey bars are the % area associated with IP reuse, and the light grey bars are the % area associated with new logic. (Source:  Semico Research)

“From a physical design tool perspective, the implications of this design trend are two-fold.  The number of cell instances in a floorplanned design block is growing.  And, in particular, the sheer number and diversity of macrocells is exploding – for example, small SRAM buffers, register files, and cell relative placement groups.”, Vinay continued.

“Exploding?”, I asked somewhat skeptically.  “Can you give me an example?” 

Vinay shared the data for a set of design blocks from a recent collaboration between Broadcom and the Cadence Innovus R&D team – the figure below includes several examples of mixed cell and macro placement block design netlists.

(From:  Jack Benzel, Broadcom, “Concurrent Placement of Macros and Standard Cells with the Mixed Placer”, CDNLive Silicon Valley conference, April 2, 2019.)

623 macros in a 6.6M instance block design.  Wow.

In the “olden days”, there were a few (relatively large) macrocells associated with a block netlist.  The SoC block micro-architect and physical design engineer worked briefly to pre-place these macros within the block floorplan.  Typically, they were placed (manually) around the block periphery to minimize the internal routing track blockage, as depicted below.

If the macros were auto-placed, they typically ended up at the block periphery as well, due to their characteristically-low pin count and thus, low contribution to the overall netlist wirelength optimization measures.  Only if the timing paths through the macro were super-critical would an internal placement be selected.

Clearly, many current SoC designs are pursuing a new paradigm.  The SoC design examples above are no longer amenable to a seeded manual macro pre-placement.  (Fortunately, the increasing number of metallization layers available in advanced process nodes enables allocation of block-level routing layers over the macro hard IP implementation, enabling a relaxed set of constraints for macro placement.)

Vinay described the recent “mixed-placement” innovations in Innovus (an apt product name).  He explained, “We re-architected the solver algorithms within Innovus placement to address the unique characteristics of current block netlists, potentially integrating many macros.  Macro-rich designs introduce a new set of constraints – for example, appropriate spacing between macros may need to be maintained for allocation of signal repowering buffers across the block and for cell insertion algorithms to address hold time issues.  And, although the mixed placement is automatic, micro-architects will want to provide (relative placement) grouping constraints to guide the algorithms to a more optimal solution.” 

Examples of potential Innovus placement constraints are given in the figure below, along with a methodology flow diagram.  Both the “mixed-placement” and “place_opt” steps in the flow diagram have been optimized for a macro-rich design netlist.

SoC designs are changing to address new (data-centric) applications – that evolution is certainly not new.  The macro-dominated nature of SoC design blocks was surprising to me – 600+ macros in a netlist exceeds my prior experience.  The roles of the micro-architects and PD engineers are changing, from focusing on macro pre-placement to defining the (minimal) set of design constraints to guide mixed-placement algorithms.  Kudos to Cadence on the recent Innovus product release, to enable more optimal implementations of these design blocks.

https://www.cadence.com/content/cadence-www/global/en_US/home/tools/digital-design-and-signoff/soc-implementation-and-floorplanning/innovus-implementation-system.html

-chipguy