Power Issues for Chip and Board

Next week there are two Apache, a subsidiary of Ansys, events. At DesignCon there are a couple of workshops on chip-package-system (CPS). In addition to Apache themselves, each of the two workshops has a number of representatives of leading edge companies doing semiconductor design. I already blogged about this in more detail here. As a general note, to find blogs about seminars, workshops, webinars and so on, click on the “seminars” button at the top of the page.

The other event, on Tuesday, is a webinar on Power Issues for Chip and Board. Brian Bailey moderates Arvind Shanmugavel, director of applications engineering for Apache, and Randy Whitel, technical marketing manager for measurement solutions from Tektronix. The first part of the webinar is pre-recorded and then there is an opportunity for live questioning of Arvind and Randy.

The summary of the webinar is:Power used to be a secondary concern when it comes to chip or system design, but with the rapid rise in importance of mobile devices, increasing chip densities, and a rise in the levels of concurrency, power consumption, power dissipation, heat dissipation, and power integrity and becoming major primary design considerations at all stages in the design flow. Many chip design techniques are making this problem more difficult, such as multiple power domains and clock gating, while high speed interfaces are creating problems with board layouts and 3D packaging techniques are raising many kinds of new challenges. Power management is an important topic for every design company to remain competitive, to increase yields and to deal with the longevity issues required for emerging industries such as automotive.

The webinar is at 10am Pacific Time on Tuesday January 31st. Registration is here. After the event, a recording of the entire webinar, including the Q&A will be available.