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Ansys, Inc.
Posted on by Paul McLellan

Low Power Webinar Series

Low Power Webinar Series
by Paul McLellan on 07-08-2011 at 4:57 pm
Categories: Ansys, Inc., EDA

At DAC 2011 in San Diego, Apache gave many product presentations. Of course not everyone could make DAC or could make all the presentations in which they were interested. So from mid-July until mid-August these presentations will be given as webinars. Details, and links for registration, are here on the Apache website.

The seminars are as below. All webinars are 11am to 12pm PDT.

  • Ultra-low-power methodology, July 19[SUP]th[/SUP]
  • IP integration methodology, July 21[SUP]st[/SUP]
  • PowerArtist: RTL power analysis, reduction and debug, July 26[SUP]th[/SUP]
  • RedHawk: SoC power integrity and sign-off for 28nm design, July 28[SUP]th[/SUP]
  • Totem: analog/mixd signal power noise and reliability, August 2[SUP]nd[/SUP]
  • PathFinder: full-chip ESD integrity and macro-level dynamic ESD, August 4[SUP]th[/SUP]
  • Chip-Package-System (CPS) convergence solution, August 9[SUP]th[/SUP]
  • Sentinel: PSI IC-package power and signal integrity solution, August 11[SUP]th[/SUP]

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