Low Power @ DesignCon 2014

Taking place annually in Silicon Valley, DesignCon is the premier educational conference and technology exhibition for electronic design engineers in the high speed communications and semiconductor communities.

Created by engineers for engineers, DesignCon is the largest gathering of chip, board and systems designers in the world and is focused on the pervasive nature of signal integrity at all levels of electronic design – chip, package, board and system. Combining technical paper sessions, tutorials, industry panels, product demos and exhibits, DesignCon brings engineers the latest theories, methodologies, techniques, applications and demonstrations on PCB design tools, power and signal integrity, jitter and crosstalk, high-speed serial design, test & measurement tools, parallel & memory interface design, ICs, semiconductor components and more.

DesignCon enables chip, board and systems designers, software developers and silicon manufacturers to grow their design expertise, learn about and see the latest advanced design technologies & tools from top vendors in the industry, and network with fellow engineers and design engineering experts.

The 2014 Technical Conference Program will consist of 14 tracks overing all aspects of electronic design, from chips through boards and systems.

Check out Who Attends DesignCon, and photos and videos from 2013!

Location
Date: Tuesday, January 28, 2014 – Friday, January 31, 2014
Location: Santa Clara, CA
EXPO– January 29 – 30, 2014
ANSYS Booth #513

Panel Sessions
System-Level Power Integrity: Tools Providers and Tool Users Engage
Date: Wednesday, January 29
Time: 3:45pm-5:00pm
Location: Ballroom G

Closing the Loop: What Do We Do When Measurements and Simulations Don’t Match?
Date: Thursday, January 30
Time: 3:45pm-5:00pm
Location: Ballroom H

Technical Papers
A Loewner-Matrix-Based Algorithm for State-Space Fitting of Frequency-Domain Data with Nonuniform Frequency Sampling
Date: Wednesday, January 29
Time: 10:15am-10:55am
Location: Ballroom K

Chip-Package-System ESD Simulation Methodology Using a Chip ESD Compact Model
Date: Thursday, January 30
Time: 2:00pm-2:40pm
Location: Ballroom J

Comprehensive Full-Chip Methodology to Verify Electromigration and Dynamic Voltage Drop on High Performance FPGA Designs in the 20nm Technology
Date: Thursday, January 30
Time: 2:50pm-3:30pm
Location: Ballroom E

About Apache
The proliferation of high-performance mobile devices — such as smartphones and tablet computers — along with the trend toward smaller electronic systems are driving engineers to design and deliver more power-efficient products with extended battery life, while still satisfying increasing performance requirements. Meanwhile, rise in power consumption and electricity costs from the IT infrastructure required to support growing mobile connectivity demands more energy-efficient products. In addition, the explosion in system-to-system wireless communications is amplifying the amount of noise within and between ICs, threatening the system with malfunction or failure.

The Apache suite provides innovative power analysis and optimization solutions that enable engineers to design and deliver products meeting stringent power specification limits, while still reliably and consistently delivering power to the entire system and mitigating failures or performance degradation caused by power-induced noise. Apache’s comprehensive suite of integrated software and methodologies spans a full spectrum of power, noise and reliability solutions, including power reduction, power and signal integrity, thermal management, and EM, ESD and EMI verification, from early in the design phase through final system sign-off.

Apache’s differentiated platforms address the unique challenges associated with various phases of the IC and electronic system design process, including RTL-level power budgeting; IP power delivery integrity validation; SoC integration and power noise sign-off; and IC package/board power and signal integrity, reliability verification and cost optimization. Apache’s accurate and compact models enable RTL-to-silicon, analog-to-digital, and chip–package–system power methodologies that facilitate effective coordination among multiple engineering teams and help to drive the electronic ecosystem.

The combined Apache and ANSYS suite provides even more functionality. It enables R&D teams to solve chip power delivery problems, package/board thermal/electromagnetic extraction, system enclosures and time-domain circuit analysis. Multiphysics capabilities impart the ability to simulate various physical phenomena across chips, packages and systems, including power optimization, signal integrity, electrostatic discharge (ESD), electromagnetic interference/electromagnetic compatibility (EMI/EMC), heat transfer, fluid dynamics and structural mechanics. The multi-user aspect provides the simulation platform and collaboration tools that enable electronics, electrical and mechanical engineers — along with managers and executives from different divisions within the organization — to collaborate in designing increasingly complex products.

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