Chip-Package-System Solution Center

One of the really big changes about chip design is the way over the last decade or so it is no longer possible to design an SoC, a package for it to go in and the board for the package using different sets of tools and methodologies and then finally bond out the chip and solder it onto the board. The three systems, Chip-Package-System have become so interrelated that everything needs to be concurrently designed. The situation only gets worse once thru-silicon-vias and interposer and true 3D designs are considered.

There are a large number of different issues that come together. The most obvious is various aspects of power, primarily getting the power into the package and distributed across the chip and then getting the heat out again, while also accounting for how the variation in temperature will affect performance. Increasingly, in a modern SoC, everything affects everything else. The temperature goes up which affects the performance which affects the power which affects the temperature.

The leader in having technology for handling this has been Apache. In fact the growth of importance of CPS and the need to adopt a much more formal analysis approach has been one of the drivers of Apache’s revenues and, clearly, one reason that Ansys acquired them.

Apache has a lot of technology in this area and historically it has required trawling their website to pull together everything that you might need. And maybe even going to the Ansys site too. But now everything is in one place the ANSYS/Apache CPS subweb:

• CPS methodology
• CPS education
• CPS new & information
• CPS blogs
• CPS user group

If you are interested (and you pretty much have to be if you are doing any of this stuff) in CPS then this is a great resource center. As a starting point, if you have not already read it there is a white paper Chip-Package-System Convergence: ANSYS and Apache Technologies for an Integrated Methodologythat is a pretty good overview of the area.