All Things Semiconductor!
Cadence has done a good job of keeping up with the needs of analog RF designs. Of course, the term RF used to be reserved for a thin slice of designs that were used specifically in RF applications. Now, it covers things like SerDes for networking chips that have to operate in the gigahertz range. Add that to the trend of combining RF and… Read More
Designers spend a lot of time looking at their layouts in 2D. This is done naturally because viewing in 2D is faster and simpler than in 3D. It helps that humans are good at extrapolating from 2D to 3D. Analysis software, such as extraction software also spend a lot of time looking at layouts in 2D. While this is fine for approximate results,… Read More
One of the really big changes about chip design is the way over the last decade or so it is no longer possible to design an SoC, a package for it to go in and the board for the package using different sets of tools and methodologies and then finally bond out the chip and solder it onto the board. The three systems, Chip-Package-System have… Read More
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Taiwan ESD Workshop Recording
Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction
Finding Your Way Through Verification (Text)
Concerned about IP security threats for your SoCs?
REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation
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REPLAY: VLSI Design Methodology Development
REPLAY: Lightspeed Data Sync – Design Workspace Problems Solved!
REPLAY: Desinging Complex SoCs and Dealing with Multiple File Formats?
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