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WIKI Multi FPGA Design Partitioning 800x100
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Have you Tried ALDEC?

Have you Tried ALDEC?
by Luke Miller on 01-22-2014 at 1:00 pm

I must admit. I was too comfortable. Let me explain, I’m a ModelSim guy from Mentor Graphics. I did not really think nor care much of the other RTL simulator options. How could someone build a better tool with respect to simulation? Let me introduce you to Aldec. Aldec was founded in 1984 by Dr. Stanley M. Hyduke. 30 years later they are still in business and growing strong. I think I heard of them once in my other life but had no time nor money to perform an evaluation of their software. Well, I get a second chance. Before I get into this I must note that my opinion has not changed, HDL coding will become less and less BUT on all FPGA design HDL coding will always be needed to mesh together all the sub-components. Aldec seems to compliment this very well including VHDL 2008 Support. So I still recommend using Xilinx’s Vivado HLS to design much of your DSP and other cores and then use Aldec to tie the wrapper and the design together. Note that these tools are all pre-synthesis tools.

Aldec today has over 30,000 active worldwide licenses. Now here is a bit of writing genius, but that is a lot of licenses. I know if you are like me, one of the major concerns when using any new tool is the health and size of a company. That is, what if I switch over to the Aldec tool suite and they go belly up? That is a realistic concern, remember the PA Semi days! I do! Let me be the first to assert that Aldec is a very healthy company, with a large user base, active software developments and world class help. That means you can pick up a phone and talk with a real person based in the United States. That is all important. They can also tailor some of the tools and license options as well. For example say your company needs 5 licenses but during design sign off, you need 50 licenses. That’s easy, they will pro rate your licenses for the time you need the extra licenses without any extra penalty. Aldec licenses are worldwide and not node locked to a particular geographic location. That equates to more cost savings.

Before I go into any deep dive, there are few tools I would like to review over the course of this year. I highly encourage you to go to the Aldec website and study what is available to accelerate your FPGA design cycle.

Active-HDL is a Windows® based, integrated FPGA Design Creation and Simulation solution for team-based environments. Active-HDL’s Integrated Design Environment (IDE) includes a full HDL and graphical design tool suite and RTL/gate-level mixed-language simulator for rapid deployment and verification of FPGA designs.

The design flow manager evokes 120+ EDA and FPGA tools, during design entry, simulation, synthesis and implementation flows and allows teams to remain within one common platform during the entire FPGA development process. Active-HDL supports industry leading FPGA devices including Xilinx and even Xilinx Zynq.

ALINT design analysis tool decreases verification time dramatically by identifying critical issues early in the design stage. Smart design rule checking (linting) points out coding style, functional, and structural problems that are extremely difficult to debug in simulators and prevents those issues from spreading into the downstream stages of design flow. The tool features highly tune-able and intuitive framework that seamlessly integrates into existing environments and helps to automate any existing design guidelines. The framework delivers configurable sets of rules, efficient Phase-Based Linting (PBL) methodology, and feature rich result-analysis tools that significantly improve user productivity and overall efficiency of the design analysis and refinement process.

Riviera-PRO™ addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate test bench productivity, re-usability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.

My next blog will walk my readers thru a real design using the ALDEC tools! Stay tuned!

lang: en_US

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