Prototyping Over 100 Million ASIC Gates Capacity

Most SoCs today are being prototyped in FPGA hardware before committing to costly IC fabrication. You could just design and build your own FPGA prototyping system, or instead choose something off the shelf and then concentrate on your core competence of SoC design.

Thanks to the FPGA vendors like Xilinx we now have FGPA prototyping platforms that can reach over 100 million ASIC gates in capacity at a reasonable cost. Aldec has created such an FPGA prototyping platform called the HES-7 and we’ve been blogging about it here on SemiWiki:

• 10 to 100X faster HDL Simulation Speeds
• ARM Cortex SoC Prototyping Platform for Industrial Applications
• Zynq out of the box, in FPGA-based prototyping
• What I Learned About FPGA-based Prototyping

These prototyping boards use two of the Xilinx Virtex-7 2000T devices which have 4 million FPGA logic cells, or about 24 million ASIC gates in capacity, and that’s not counting the RAM and DSP resources available. You can then connect up to four of these boards together, so your total ASIC gate count is 96 million plus the RAM and DSP resources, crossing the 100 million gate barrier.

The popular ARM architecture is also available as the dual-core Cortex-A9 MPCore using the Xilinix Zynq-7000 device. You can even run open-source Linux, Android and FreeRTOS available from Xilinx on these prototyping boards, enabling your hardware and software teams to verify more quickly.

The speed of the HES-7 is fast enough (up to 1GHz or so) that you can prototype SoCs designs for: Video, Communications, Control Systems and Bridging. Add your own hardware to this board using the daughterboard connectors, which are open and fully specified. See a full list of features here.

Further Reading

There’s a White Paper: ARM Cortex SoC Prototyping Platform for Industrial Applications

Aldec at DAC
At DAC next month in Austin you have a chance to meet with the best in brightest in EDA and Semi IP all in one convenient place and time. Consider signing up for the 45 minute Technical Session at Aldec in booth #2225:

• Session 01: Prototyping Over 100 Million ASIC Gates Capacity

lang: en_US