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Calypto, in Three Part Harmony

Calypto, in Three Part Harmony
by Paul McLellan on 05-11-2013 at 8:00 am

 As Julius Caesar said, “Gallia est omnis divisa in partes tres.” All Gaul is divided into 3 parts. Calypto is similar with three product lines that work together to provide a system level approach to SoC design. Two of those product lines are not unique, in the sense that similar capabilities are available from a handful of other companies, but the original core technology that Calypto worked on when it was first founded, sequential logical equivalence checking (SLEC), is.

The three technologies that make up Calypto are:

SLEC: in the same way as logical equivalence checking proves that a gate-level netlist is equivalent to the RTL of a design (and thus that synthesis did its job correctly), SLEC proves that the output RTL is equivalent to the C/C++/SystemC of a design (and thus HLS did its job correctly). When Calypto was founded, the CEO was Devadas Varma who I’d worked with at Ambit, and what he and his team proposed doing seemed beyond the frontier of what was possible, but they succeeded and today’s SLEC product is the result.

 Catapult: this is high-level synthesis (HLS) technology that was originally a Mentor product but which was spun out of Mentor and into Calypto along with some people (and having worked for Greg Hinckley, the COO/CFO of Mentor when I was at VLSI I’m sure it was a sophisticated financial transaction too). Since HLS requires SLEC for verification (and it is probably even more important than for RTL/gates since HLS is less mature technology) this transaction made a lot of sense from a sales point of view, since one salesperson could sell both products from one company. Plus the Calypto sales team is focused on this market, whereas Mentor has a huge product line and it is easy for products to suffer from lack of focus with sales.

PowerPro: this performs power analysis and sequential power optimization. Since this alters the sequential behavior of the design, this also requires SLEC to verify that the changes didn’t alter the functionality, merely reduced the power. The tool works by identifying register transfers that will not alter the results of the design, and generates a small amount of additional circuitry to suppress them.

Calypto has integrated these three technologies to offer industry’s only HLS solution that can synthesize power optimized RTL from C++ or SystemC and formally verify the synthesized RTL against the original C++ or SystemC. It is almost a general rule in EDA that optimizations done at a high level are more powerful than at a lower level. By moving up to a level above RTL, the designer has more options for power-performance-area (PPA) tradeoffs, and by having power optimization under the hood of high-level synthesis, it makes those tradeoffs simpler to explore.

You can see these three products at DAC at the Calypto booth, #1247. There is a complete list of suite demos that you can register for here.

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