Rad Hard Circuit Design and Optimization for Space Applications

The Brazilian Ministry of Science and Technology (MCTIC) has a research unit, Renato Archer Information Technology Center (CTI), and two of their IC engineers presented at the MunEDA User Group meeting this May on the topic of designing Latching Current Limiter (LCL) circuits for space applications with RHBD (radiation-hardened by design) techniques.

Small satellites operate in a hostile environment but do not have adequate shielding due to their low weight requirement. Therefore, electronic circuits must use techniques for radiation-hardening by process (RHBP) or by design (RHBD).

The LCL is a smart power switch that protects an electronic system to isolate faults in power distribution by limiting the current. This protects space-based electronics in a satellite from radiation effects like

• Total Ionizing Dose (TID)
• Displacement Damage (DD)
• Single Event Effects (SEE)
• Single Event Latch-up (SEL)

In their MUGM2023 contribution, the authors showed three LCL designs and how MunEDA WiCkeD contributed to their RHBD circuit optimization:

• Control circuit in 0.6u SOI technology with discrete power transistor Infineon IRF4905
• Control circuit and power transistor in 0.6u SOI technology multi-chip module
• Control circuit in 0.18u standard CMOS technology with discrete GaN power transistor GS61008T

In order to mitigate radiation effects by design (RHBD), several decisions were made:

• Trench isolation and guard rings to reduce leakage currents
• Replace standard MOS transistor layout with enclosed-layout transistors (ELT) to eliminate drain-source leakage caused by the accumulation of charges in the oxide region (TID)
• Device redundancy for increased fault tolerance
• Use MunEDA WiCkeD to optimize the LCL circuits’ performance and robustness against parameter and process variation

Two circuit versions were designed, one with standard transistors and the other using Radiation Hardened By Design (RHBD) techniques.

EDA tools used were Cadence Virtuoso for schematics, MunEDA WiCkeD for optimization, and Cadence Assura or Siemens Calibre for DRC/LVS. The advantages of using WiCkeD for this project were:

• Shorter design time and engineering effort
• All critical blocks of the LCL optimized for performance and robustness: operational amplifiers, bandgap voltage reference circuits, current references, comparators, drivers, current sensors, control loop, timers, telemetry circuits, thermal shutdown, and voltage regulators.
• Large circuit control loop optimization: limiting the short-circuit peak current made an inductor next to the power transistor necessary, introducing stability issues that had to be resolved by optimizing the whole control loop with WiCkeD
• Improved accuracy
• Make Rad Hard By Design with ELT and redundancy perform like the standard transistor version
• All LCL circuits worked as designed

Test chips for the two LCL approaches were fabricated and then tested. The RHBD circuit performed similarly to the standard transistor circuit, so both LCL circuits worked properly under different loads and power transistors. The short-circuit peak current was eliminated, keeping the entire system safe. They plan to perform radiation tests to validate the hardening circuit techniques used.

Summary

Using a RHBD approach was shown to be effective in an LCL circuit to eliminate short-circuit peak currents, keeping an electronic system safe from failure modes while operating in space. Both the standard transistor and ELT approaches were optimized using the MunEDA WiCkeD tool, as part of a multi-vendor EDA tool flow.

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