Optical I/O Solutions for Next-Generation Computing Systems

According to DARPA the fraction of total power consumed in semiconductors for I/O purposes as been growing rapidly and is creating an I/O power bottleneck. It has reached the point where it needs to be addressed with new technologies and approaches. Interestingly, while the energy density, as measured by pJ/bit for short reach IO – such as chip to chip in the same system – is low, there are so many more connections and higher data volumes that the overall energy required is often higher than in rack to rack connections. Dries Vercruysse, Senior Photonics Design Engineer at Ayer Labs, recently gave a talk at the Ansys Ideas Digital Forum 2021 on how they were motivated to use optical technology for chip to chip communication. He pointed out that the energy efficiency density of longer reach connections has long benefited from the use of optical technology.

There are many hurdles to taking photonics methods for board to board and scaling them so they are effective and efficient enough for use between individual packages. Dries describes how Ayer Labs has developed a solution based on optical modulation using micro-ring resonators.  They have created tunable voltage-controlled resonators that are 1000x smaller than optical devices in traditional ethernet transceivers and are compatible with 300nm CMOS technology. An off-chip laser is coupled from fiber to chip via a vertical grating coupler and then amplitude modulated by varying the bias voltage across the resonator.

Because resonators that operate at different wavelengths can be created by varying physical parameters, one fiber can support many signals in parallel via wavelength division multiplexing (WDM). A single off-chip laser can provide the light source needed for many chips. The Ayer Labs chiplet contains multiple drivers and receivers that then interface externally through short fiber connections to other chips and can be tightly integrated with FPGAs via in-package system-on-chip (SoC).

Dries talked about a Link Demo they performed that connected two chips that each used the Ayer Labs TeraPHY CMOS Optical IO chip. With a remote light source and a bi-directional link, they achieved energy use of <5pJ/bit for both 16Gbps and 25Gbps. The fiber operated at ~5.3 microwatt average power/lambda. During the demo they transferred 104.165 terabits of data without any errors.

Creating this system required extensive simulation of the electrical, physical and optical performance characteristics in their TeraPHY chiplet. For instance, the resonator has semiconductor junctions, optical paths, and even a small thermal heater to help rigidly control the thermal environment. According to Dries this was a perfect example of Multiphysics design. Time frames for each domain were orders of magnitudes apart as well. From picoseconds for the optical, to microseconds for the thermal. They used a wide range of Ansys tools to facilitate their development. The waveguide alone required GPU accelerated IOSMF FDTD simulations with over 1.6 trillion grid points. This was accomplished using the cloud compute environment offered by Ansys.

Ayer labs has already had design success and notable design wins leading to integrations into advanced SoC packages. Dries highlighted their work with Intel FPGAs, including a design that is on a standard PCIe card. Previously, the use of optical fiber was a pipe dream for chip to chip communications. Ayer has shown that it is not only feasible, but it can be effective. The key to their development was having the ability to fully model Multiphysics behavior in a complex environment. The full presentation from the Ansys Ideas Digital Forum 2021 is available for viewing here.

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