CEO Interview with Chuck McClish of of Lattrex Inc.

I spent 15 years at Microchip doing RTL design, UVM verification, synthesis, place-and-route, STA, analog modeling, EDA tool bringup, at one point or another I’d sat in nearly every seat of the flow. It was work I genuinely enjoyed, until a reorg moved me into a group and a role I didn’t. Eventually I decided I was done, and I walked out without a plan to take some time and figure out what was next.

While working on various unrelated projects, I found myself taking a long, hard look at how silicon actually gets designed today. Every chip is essentially a custom work of art. Each one is enormously complex, fragile, and typically doesn’t scale gracefully.

So I ran a thought experiment and took inspiration from biology. Nature has mastered scaling, from an amoeba to a blue whale and everything in between, using resilient, asynchronous systems: fine-grained parallelism and local communication that keep extraordinarily complex organisms running with no centralized control over any individual process. It does that with individual cells organized in a three-dimensional matrix, communicating over various electrical and chemical processes.

Now, I couldn’t build something as complex as a living cell in silicon, but I could build a simplified model that emulates the computation paradigm. What resulted was the company’s first prototype, which is essentially a compute substrate where programs grow, not unlike fungal mycelium spreading across a petri dish. I designed and taped out the first prototype chip, Kyttar (KIT-ar), solo in 3 months and have been working on tooling, applications, and customer discovery since then.

Lattrex is built on a bet, and the bet is that the industry took the more complicated road when a simpler one was right there. For decades chip design has optimized around the clock: bigger, faster, more intricate synchronous machines, every one as unique as the team that built it. Asynchronous, self-timed design has always been the road not taken, not because it didn’t work, but because so few people bothered to walk it. The tooling, the talent, and the momentum all went the other way.

For high speed serialized workloads, this makes sense. But there is a class of applications requiring enormous amounts of real-time, parallel processing that have to run in tight power and size budgets where this paradigm doesn’t fit well. Our conviction is that a homogeneous, self-timed array of simple computation cells handles that class of problem better than the clocked, monolithic parts the industry reaches for by default. Its radical simplicity and sameness are exactly what lets it scale, manufacture, and be verified in ways a complex design never can.

Right now Lattrex is a fabless startup that’s mostly me and a lot of tooling, with a 120-cell prototype chip coming back from the fab this fall.

As we move toward the 2030s, more and more real-time signal processing is being pushed out to places with almost no power or space to spare. The tools we hand people for that are a DSP or FPGA, and each forces a bad trade. A DSP is approachable but fundamentally serial, so you hit a throughput wall. An FPGA is parallel and powerful but you pay for it in clock-tree power, in HDL and timing closure, and in long design cycles. Neither was built for “process a lot of channels at once, at very low power.”

We think the missing option is the reconfigurable array done asynchronously, and that the reason it’s missing is simply that nobody committed to making it usable. We are building this third path and making it something any engineer can pick up and build applications with.

Anywhere the problem is “many channels at once, in a tight power and size budget”. We identified software-defined radio as our beachhead and initial focus. Adjacent to that is spectrum monitoring, multi-channel phased-array receivers, and electronic warfare related defense applications. There’s also a resilience angle in harsh environments. Because the array is a sea of identical cells, a defective one can be routed around at programming time instead of designed around with redundancy hardware. For reliability- and radiation-sensitive work, that homogeneity is a major benefit. Any other ideas out there? We’d love to hear about them!

Power and size in the field, and development time in the lab, usually both at once. The people I talk to in the SDR and defense world are fighting SWaP budgets and long, painful toolchain cycles simultaneously. They want to change a waveform without rebuilding a bitstream, add channels without growing the power envelope, and get from idea to working hardware in less than a quarter.

The honest comparison is against FPGAs and DSPs, because that’s what people reach for today. As one of my professors used to say, “there are no free lunches in engineering,” and that’s true for us as well. If you need to push one channel as fast as possible, a DSP or an FPGA will win vs our architecture today. We’re playing a different game. Our architecture sits in a category you could call a coarse-grained reconfigurable array, between a DSP’s flexibility and an FPGA’s parallelism, with the differentiation being that it’s self-timed and homogeneous. That combination is where our whole thesis pays off: for many parallel, mostly-idle channels in a constrained power and size budget, the idle power is the story, and those properties compound instead of trading off against each other. The deeper differentiation is the manufacturing and verification model, one simple cell, verified once, tiled endlessly, which is a fundamentally different bet than the ever-more-complex path the rest of the industry is on.

The most important thing we’re building today isn’t the next chip, it’s making this class of architecture usable. An async reconfigurable array is worthless if nobody can program it, so tackling programmability is the first thing I’m doing. Our development environment, placeKYT (place-kit), lets you build a design in GNU Radio Companion, import it, and place, route, and simulate it against a cycle-accurate model. It enables an engineer to watch the data flow through the array and debug it at the instruction level, while also getting speed and power performance numbers. Seeing the computation move through space turns out to be the fastest way to understand why the architecture is different. When first silicon returns this fall, that same flow drives the real chip. Past that, the roadmap is to develop a performance optimized cell for production on a modern FinFET node with far more cells on a single die, and eventually pairing the array with an analog front-end die so the whole signal chain, antenna to bits, lives in one package.

Today it’s early and open. placeKYT is publicly available, so the best first step is to download it and build something. The examples run real demos, from a simple gain block to single-sideband, AM, and FM transceivers and a BPSK modem, all placed, routed, and simulating end to end. From there I’m having conversations with potential design partners and customers, and I’m running an SBIR/STTR track on the defense side. As we grind through the customer discovery process, we love to hear from engineers working in our target markets. Reach out to us on our website, X, or LinkedIn. Good, bad, or ugly, we’d love to hear from you!