Interview with Simon Davidmann, AI + EDA Researcher and Former CEO of Imperas

Simon Davidmann is a renowned EDA industry pioneer and serial technology entrepreneur with more than 40 years of experience in simulation and verification. After Synopsys acquired Imperas, which he founded in 2005, he was Synopsys Vice President responsible for Processor Modeling and Simulation. He left Synopsys in 2025 and is now an AI + EDA researcher at Southampton University, UK.

Davidmann has an illustrious track record in EDA. In fact, he founded Co-Design and co-architected the Superlog language as a superset of Verilog that became IEEE standard SystemVerilog. It was sold to Synopsys in 2002. Each of the companies Davidmann founded or was a key staff member of since the early 1980s has been acquired by a larger EDA tools firms:

• Gateway Design Automation was acquired by Cadence in 1991
• Chronologic Simulation (developer of VCS), was sold to Viewlogic in 1995—and subsequently acquired by Synopsys
• Ambit Design Systems was sold to Cadence in 1998 for $280 million

Tell us about what you’ve been up to recently.

For the past many years, I was CEO of Imperas where we developed reference models of processors like Arm, and RISC-V, for use in Virtual Platforms, like Open Virtual Platforms (OVP) and Synopsys Virtualizer. With the evolution of RISC-V, we developed ImperasDV, the leading RISC-V verification technology that pioneered asynchronous lock-step oracle verification to find the most complex bugs. We were acquired into Synopsys in 2023 and I have now left and am doing research in a UK university.

What interested you into becoming AI + EDA researcher?

When we started working with RISC-V back in 2016, we found more and more users of our technology were building custom silicon to run their custom workloads. Many (e.g. Nvidia, Denso) were building what we would now call AI accelerators. I started being aware of industry adoption of AI several years ago and got more interested and presented several conference papers/presentations on the use of our technology with AI hardware.

Part of this interest was simply learning how we could handle such large amounts of simulation needed by this AI hardware. Later this interest became more verification focused. First, how could Machine Learning (AI) algorithms/models be used to assist with the verification effort. And then, I thought traditional approaches to verification were not likely to cope with the future complexity of hardware architectures that were being envisaged and I wanted to explore different approaches to verification based around the power of the evolving ML/AI.

What are some of your early findings?

For years, EDA has done a great job in optimizing design and verification algorithms. In the last 10 years, a lot of tools have adopted advanced optimization maths and machine learning to produce excellent results. I recently presented at a DVClub event and reviewed products and academic adopters of ML in verification where results ranged from 85% less RTL simulation required, to 10% better coverage achieved. There is real use of ML/AI already in improving existing tool efficiency and methodologies.

Do any surprise you?

Yes, I think the chip design ecosystem is just “Blinded by the LLMs headlights.”

I see there is a Dilemma: The chip design ecosystem is currently using AI to accelerate what it already knows how to do. The real opportunity with AI is to completely transform what and how it is possible to design and verify. It is a systemic tension where every individual player acting rationally guarantees a collectively wrong outcome. By simply injecting AI into legacy processes, they are just shovelling faster, not changing the shape of the mountain.

Along with my Dilemma, I have a related Test: Does AI fundamentally change what you can design and verify, or does it just accelerate how fast you run what you already do? If it only does the latter, it fails the Test.

Are there opportunities for EDA startups that aren’t agentic AI tools?

Absolutely. Real breakthrough will come from a holistic approach that rethinks the toolchain itself. Unifying design, verification, and implementation allows AI to reason across the entire stack, rather than just shuttling between the fragmented silos built for humans over the last four decades. Today’s agentic AI is simply a band-aid on the way to a genuine design/verification/implementation architectural reset.

I am looking forward to the next generation…

How can SemiWiki readers contact you to learn more?

I am at DAC in Long Beach Jul 26-29 visiting vendors, exploring papers, walking the exhibitor isles and expressing my views on a couple of panel sessions. Readers should just stop me and say hello.

Presentations and Videos

Here are links to two presentations I gave at DVClubs in Bristol and Edinburgh Universities in the UK on AI+EDA:

• https://alpinumconsulting.com/wp-content/uploads/Simon-Davidmann-DV-Club-Bristol-AIEDA-Davidmann28-Jan-2026FINAL.pdf
• https://alpinumconsulting.com/dv-club-edinburgh-june-2026/

I have co-authored several videos on the use of Simulation/Verification for AI/ML silicon at various RISC-V summits/forums:

• 2019 Avoiding Amdahl’s Law for AI & ML Compute – explains simulation of accelerators

https://www.youtube.com/watch?v=kKKkxyuVXpM

• 2020 SoC Architectural Exploration for AI and ML accelerators – demonstrated a simulation of several RISC-V and Arm processors running the AlexNet

https://www.youtube.com/watch?v=xYrWKqN1onY

• 2020 Rolling the Dice with Random Instructions is the Safe Bet on RISC-V Verification (Imperas, Google, Metrics)

https://dvcon-proceedings.org/wp-content/uploads/rolling-the-dice-with-random-instructions-is-the-safe-bet-on-risc-v-verification.pdf

• 2021 Software Development for ML and RISC-V Vector Accelerators – configurable simulation

https://www.youtube.com/watch?v=aAoFQX2RavQ

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