whitepaper semiwiki ad jitter
WP_Term Object
(
    [term_id] => 14418
    [name] => Prototyping
    [slug] => prototyping
    [term_group] => 0
    [term_taxonomy_id] => 14418
    [taxonomy] => category
    [description] => FPGA based Prototyping
    [parent] => 0
    [count] => 102
    [filter] => raw
    [cat_ID] => 14418
    [category_count] => 102
    [category_description] => FPGA based Prototyping
    [cat_name] => Prototyping
    [category_nicename] => prototyping
    [category_parent] => 0
    [is_post] => 
)

2026 Outlook with Ying J Chen of S2C

2026 Outlook with Ying J Chen of S2C
by Daniel Nenni on 01-22-2026 at 6:00 am

Ying J Chen of S2C

I’m Ying J Chen, VP of S2C. S2C is a leading global supplier of FPGA prototyping solutions for advanced SoC and ASIC designs, holding the second largest share of the global prototyping market. Founded in 2003, the company has supported more than 600 customers, including 11 of the top 25 semiconductor companies worldwide, with teams… Read More


Accelerating Advanced FPGA-Based SoC Prototyping With S2C

Accelerating Advanced FPGA-Based SoC Prototyping With S2C
by Daniel Nenni on 01-18-2026 at 12:00 pm

Prodigy S8 100 Logic Systems

Having spent a significant amount of my career in EDA and IP I can tell you first hand how important picking the right prototyping partner is. I have known S2C since my interview with CEO Toshio Nakama in 2017. It has been a pleasure working with them and I look forward to seeing an S2C update at DVCon the first week of March here in Silicon… Read More


There is more to prototyping than just FPGA: See how S2C accelerates SoC Bring-Up with high productivity toolchain?

There is more to prototyping than just FPGA: See how S2C accelerates SoC Bring-Up with high productivity toolchain?
by Daniel Nenni on 01-15-2026 at 10:00 am

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System-on-Chip designs continue to grow in scale and interface diversity, placing greater demands on prototype capacity, interconnect planning, and bring-up efficiency. These challenges arise not only in large multi-FPGA programs but also in smaller designs implemented on a single device or a small FPGA cluster. In all cases,… Read More


S2C, MachineWare, and Andes Introduce RISC-V Co-Emulation Solution to Accelerate Chip Development

S2C, MachineWare, and Andes Introduce RISC-V Co-Emulation Solution to Accelerate Chip Development
by Daniel Nenni on 12-16-2025 at 10:00 am

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MachineWare, and Andes Technology today announced a collaborative co-emulation solution designed to address the increasing complexity of RISC-V-based chip design. The solution integrates MachineWare’s SIM-V virtual platform, S2C’s Genesis Architect and Prodigy FPGA Prototyping Systems, and Andes’ high-performance… Read More


FPGA Prototyping in Practice: Addressing Peripheral Connectivity Challenges

FPGA Prototyping in Practice: Addressing Peripheral Connectivity Challenges
by Daniel Nenni on 11-19-2025 at 10:00 am

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Modern chip design verification often encounters challenges when connecting peripherals, primarily due to drastic differences in operating speed or hardware limitations. Designs running on hardware emulators or FPGA prototyping platforms typically operate at clock frequencies of tens of megahertz, and in some cases even… Read More


AI Everywhere in the Chip Lifecycle: Synopsys at AI Infra Summit 2025

AI Everywhere in the Chip Lifecycle: Synopsys at AI Infra Summit 2025
by Kalar Rajendiran on 09-30-2025 at 10:00 am

Godwin Talk Summary AI Infra Summit 2025

At the AI Infra Summit 2025, Synopsys showed how artificial intelligence has become inseparable from the process of creating advanced silicon. The company’s message was clear: AI is an end-to-end engine that drives every phase of chip development. Three Synopsys leaders illustrated this from distinct vantage points. Godwin… Read More


S2C Advances RISC-V Ecosystem, Accelerating Innovation at 2025 Summit China

S2C Advances RISC-V Ecosystem, Accelerating Innovation at 2025 Summit China
by Daniel Nenni on 08-13-2025 at 10:00 am

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Shanghai, July 19, 2025 — S2C, a leader in functional verification, showcased its latest digital EDA solutions and key partnerships with BOSC, Xuantie, and Andes Technology at RISC-V Summit China 2025, highlighting its contributions to the ecosystem. The company also played a leading role in the EDA sub-forum, with VP Ying… Read More


Double SoC prototyping performance with S2C’s VP1902-based S8-100

Double SoC prototyping performance with S2C’s VP1902-based S8-100
by Daniel Nenni on 07-14-2025 at 10:00 am

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As AI, HPC, and networking applications demand ever-higher compute and bandwidth, SoC complexity continues to grow. Traditional 50M ASIC equivalent gate FPGA prototyping systems have become less effective for full-chip verification at scale. Addressing this challenge, S2C introduced the Prodigy S8-100 Logic system, powered… Read More


Enabling RISC-V & AI Innovations with Andes AX45MPV Running Live on S2C Prodigy S8-100 Prototyping System

Enabling RISC-V & AI Innovations with Andes AX45MPV Running Live on S2C Prodigy S8-100 Prototyping System
by Daniel Nenni on 06-24-2025 at 6:00 am

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Qualifying an AI-class RISC-V SoC demands proving that wide vectors, deep caches, and high-speed I/O operate flawlessly long before tape-out. At the recent Andes RISC-V Conference, Andes Technology and S2C showcased this by successfully booting a lightweight large language model (LLM) inference on a single S2C Prodigy™ S8-100… Read More


Cost-Effective and Scalable: A Smarter Choice for RISC-V Development

Cost-Effective and Scalable: A Smarter Choice for RISC-V Development
by Daniel Nenni on 04-25-2025 at 6:00 am

Vast library of 90+ Prototype Ready IP

The RISC-V ecosystem is witnessing remarkable growth, driven by increasing industry adoption and a thriving open-source community. As companies and developers seek customizable computing solutions, RISC-V has become a top choice. Providing a scalable and cost-effective ISA foundation, RISC-V enables high-performance… Read More