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Optimize Your Interconnect & Design at System Level for Best Results

Optimize Your Interconnect & Design at System Level for Best Results
by Pawan Fangaria on 09-16-2014 at 7:00 am

As the SoC design size, complexity and functionality keeps on increasing with multiple IPs packed together and design time and time-to-market keeps on decreasing amid critical constraints on PPA, there is no other alternative than to do the design first-time-right not to miss the window of opportunity. And that could be possible… Read More


Interface IP Protocols: Status

Interface IP Protocols: Status
by Eric Esteve on 09-16-2014 at 3:52 am

If your company develops Design IP to support well-known protocols like USB, PCIe, HDMI, DDRn memory controller, MIPI specification (and more), it’s crucial to know your competition, the market size by segment, and even more important the market potential by segment. The latest can be obtained by the Compound Annual Growth Rate… Read More


Safer SoCs for safer driving

Safer SoCs for safer driving
by Don Dingee on 09-14-2014 at 4:00 pm

Flip on the TV, and a car commercial is bound to pop up shortly touting one of two technological aspects. One is center stack integration of smartphone-style applications. The other is advanced driver assistance systems (ADAS) featuring cameras, radar, and other sensors helping cars … Read More


Sidense overlays OTP on TSMC 16nm FinFET

Sidense overlays OTP on TSMC 16nm FinFET
by Don Dingee on 09-13-2014 at 7:00 am

Process shrinks, which have served us well for most of the Moore’s Law journey, are reaching their limits. For switching transistors, the biggest problems of leakage current and gate oxide vulnerability in planar MOSFETs have led the industry to new 3D microstructures such as FinFET. For non-volatile memory, the problem is generally… Read More


Design & EDA Collaboration Advances Mixed-Signal Verification through VCS AMS

Design & EDA Collaboration Advances Mixed-Signal Verification through VCS AMS
by Pawan Fangaria on 09-07-2014 at 8:00 pm

Last week it was a rare opportunity for me to attend a webinar where an SoC design house, a leading IP provider and a leading EDA tool provider joined together to present on how the tool capabilities are being used for advanced mixed-signal simulation of large designs, faster with accuracy. It’s always been a struggle to combine design… Read More


EDA Plus ARM Equals Big Views!

EDA Plus ARM Equals Big Views!
by Daniel Nenni on 09-07-2014 at 9:00 am

In looking at the SemiWiki analytics, one of the top search terms that brings traffic to our site is ARM, just about anything ARM. In fact, that’s what the next SemiWiki book will be about. Yes, ARM is that interesting. While EDA is also one of our top search terms, EDA+ARM will get the most views, absolutely. And let’s face it, bloggers… Read More


Momentum Builds For 64-bit ARMv8-A

Momentum Builds For 64-bit ARMv8-A
by Eric Esteve on 09-03-2014 at 2:55 am

No doubt about it, the summer break has ended, it’s time for releasing big announcement, like this one from ARM “Momentum Builds For the Next Generation of ARM Processors”. In fact, the key information is about ARMv8-A market adoption. A total of 27 companies have signed agreements for the company’s ARMv8-A technology as… Read More


MIPS 64 bit CPU Architecture

MIPS 64 bit CPU Architecture
by Eric Esteve on 09-02-2014 at 4:47 am

Imagination Technologies has just launched the 5[SUP]th[/SUP] generation of MIPS CPU core, the 64-bits Warrior, or I6400 family, offering a total compatibility with the 32-bit previous architecture. MIPS Warrior I-class processor cores offers 64-bit processing in applications including embedded, mobile, digital consumer,… Read More


New details on Altera network-on-FPGA

New details on Altera network-on-FPGA
by Don Dingee on 08-28-2014 at 4:00 pm

Advantages to using NoCs in SoC design are well documented: reduced routing congestion, better performance than crossbars, improved optimization and reuse of IP, strategies for system power management, and so on. What happens when NoCs move into FPGAs, or more accurately the SoC variant combining ARM cores with programmable… Read More


Opting for ARM software scalability

Opting for ARM software scalability
by Don Dingee on 08-26-2014 at 12:00 pm

Behind much of the success of ARM architecture is a scalable software model, where in theory the same code runs on the smallest member of the family to the largest. In practice, there are profiles, and a variety of hardware execution units, and resource constraints in low power scenarios that enter the picture. As a result, operating… Read More