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FPGA
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CCIX shows up in ARM CMN-600 interconnect

CCIX shows up in ARM CMN-600 interconnect
by Don Dingee on 09-30-2016 at 4:00 pm
Categories: Arm, FPGA, IP

All the hubbub about FPGA-accelerated servers prompts a big question about cache coherency. Performance gains from external acceleration hardware can be wiped out if the system CPU cluster is frequently taking hits from cache misses after data is worked on by an accelerator.

ARM’s latest third-generation CoreLink CMN-600 … Read More

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Up front phases improve CDC analysis

Up front phases improve CDC analysis
by Don Dingee on 09-19-2016 at 4:00 pm
Categories: Aldec, EDA, FPGA

Many tools find clock domain crossings (CDCs) in FPGA designs. Some don’t find the right ones since they don’t comprehend things like in-house synchronizer constructs. Some find too many based on misunderstanding intent, inaccurate constraints, and other factors that lead to noise.… Read More

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VHDL parameterized PWM controller

VHDL parameterized PWM controller
by Claudio Avi Chami on 09-18-2016 at 7:00 am
Categories: FPGA

Digital outputs can either go ON or OFF. Analog signals, on the other side, can smoothly assume multiple values in a range. There is a technique that emulates analog behavior with a digital output. That technique is PWM, namely, Pulse Width Modulation. It can be implemented as pulses with varying ‘high’ and ‘low’… Read More

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Intel Stratix 10 MX FPGA Highlights

Intel Stratix 10 MX FPGA Highlights
by Claudio Avi Chami on 09-15-2016 at 7:00 am
Categories: FPGA, Intel Foundry

These days, FPGAs are fairly complex pieces of silicon. Being that the case, it would take several articles even to put a summary of the features embedded in high-end FPGA devices. Hence, in this article, I will concentrate in just one feature, namely, the new embedded memory blocks of the recently released Intel-Altera Stratix… Read More

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Mentor Functional Verification Study 2016

Mentor Functional Verification Study 2016
by Bernard Murphy on 09-14-2016 at 7:00 am
Categories: EDA, FPGA, Siemens EDA

Periodically, Mentor commissions a user/usage survey on Functional Verification, conducted by the Wilson Research Group, then they publish the results to all of us, an act of industry good-citizenship for which I think we owe them a round of thanks. Harry Foster at Mentor is breaking down the report into a series of 15 blogs. He’s… Read More

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SoC FPGAs for IoT Edge Computing

SoC FPGAs for IoT Edge Computing
by Claudio Avi Chami on 09-11-2016 at 4:00 pm
Categories: FPGA, IoT

One of the reasons for the explosive growth of IoT is that embedded devices with networking capabilities and sensor interfaces are cheap enough to deploy them at a plethora of locations.

However, network bandwidth is limited. Not only that, but also, the latency of the network can be of seconds or minutes. By the time the sensor data… Read More

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FPGAs at Deep Machine Learning

FPGAs at Deep Machine Learning
by Claudio Avi Chami on 09-08-2016 at 12:00 pm
Categories: FPGA

The concept of machine learning is not new. Attempts at systems emulating intelligent behavior, like expert systems, go as far back as the early 1980’s. And the very notion of modern Artificial Intelligence has a long history. The name itself was coined at a Dartmouth College conference (1956), but the idea of an “electronic… Read More

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Keeping your design files organized

Keeping your design files organized
by Claudio Avi Chami on 09-07-2016 at 7:00 am
Categories: FPGA

Men marry women wishing they will never change, but they do.Women marry men wishing they will be able to change them, but they don’t.

When I was young, even during my University studies, I was a real disaster in anything related to order. My room was always a mess. Whenever my mother or any other would try to change my ways (even… Read More

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Pseudo random generator tutorial in VHDL (Part 3/3)

Pseudo random generator tutorial in VHDL (Part 3/3)
by Claudio Avi Chami on 09-04-2016 at 4:00 pm
Categories: EDA, FPGA



On the first two chapters of this Tutorial we started with a simple LFSR module and added a test bench. Then, on chapters three and four we upgraded our module with some features and learned to export the test bench data to files.
… Read More