Mach42 spun out of the Department of Physics at the University of Oxford in 2019 with a mission to establish software tools capable of drastically accelerating expensive physics simulations while supporting complex computational workflows. The prototype tools were successfully applied in the emulation of extreme states … Read More
Synopsys at Design Automation Conference 2026
Synopsys is catalyzing the era of pervasive intelligence with comprehensive engineering solutions spanning silicon design, IP, and simulation and analysis. At this year’s Design Automation Conference (DAC), the company will showcase innovations transforming silicon and systems development for a wide range of applications… Read More
DAC 2026: Join Accellera for a dynamic luncheon exploring how artificial intelligence is reshaping the standards landscape for design and verification.
Accellera Systems Initiative invites the design and verification community to join us at the 2026 Design Automation Conference for a focused technical luncheon, “Embracing AI for Advanced Design and Verification,” on Tuesday, July 28, from 12:30–1:45 p.m. at the Long Beach Convention Center, Meeting Room 104C.
Artificial… Read More
MooresLabAI at DAC 2026: Why the Future of Semiconductor Engineering Is Agentic, Not Just Generative
For decades, semiconductor innovation has been constrained not by imagination, but by engineering capacity. While transistor density has continued to advance, the process of building chips has remained fundamentally manual, fragmented across specifications, RTL, verification, debugging, coverage analysis, and signoff.… Read More
Caspia Technologies is pioneering a new, agentic chip and system security approach at DAC 2026
Caspia’s advanced tools and agents blend seamlessly with existing design flows to add expert-level security verification capabilities for all design teams. Founded in 2020 and headquartered in Gainesville, Florida, Caspia brings together expertise in chip design, fabrication, test, and verification with a deep understanding… Read More
Webinar: Caspia Shows You How to Fix Security Flaws Before It’s Too Late
Chip-level vulnerability is becoming an existential threat for virtually all systems. The time to ensure your chip designs are resistant to these attacks is now. Caspia presented a webinar recently that provides important information on how to build attack-resistant chips. If you missed it, don’t worry. A replay link is coming.… Read More
WEBINAR: Why Google Cloud NetApp Volumes Matter for Modern EDA Workloads
In this webinar, Google Cloud and NetApp explore how semiconductor companies can address the growing infrastructure demands of modern Electronic Design Automation (EDA) workflows. As process technologies continue to advance and chip designs become increasingly complex, engineering teams require scalable, high-performance… Read More
How to Free Yourself from Inconsistent Engineering Documentation Before It’s Too Late
Embedded systems programs often fail because critical engineering documentation drifts out of alignment over time and distance. This results in a team that is correctly following the wrong instructions. All forms of engineering documentation suffer from this problem, and it really is the silent killer of many programs.
llmda.ai… Read More
How Samtec Blazes a Trail to 224/448 Gbps at DesignCon 26
I recently covered what Samtec was doing at DesignCon 26. Samtec has a tendency to dominate any show it attends in multiple dimensions. The prior post focused on the company’s contributions to the technical agenda and the high-profile experts in attendance. While all that is interesting and valuable, attending a large show like… Read More
Webinar: Faster Design Spec to Implementation using IP-XACT
As SoC design flows grow increasingly complex, IP-XACT has become a cornerstone standard throughout the entire development lifecycle: from architecture specification to design assembly and verification. Its growing adoption is reflected in the standard’s continuous evolution, from the 2009 release through 2014… Read More


Intel Wildcat Lake: Right-Sizing Silicon Without Sinking Performance