The SPIE Advanced Lithography + Patterning Symposium recently concluded. This is a popular event where leading researchers gather. Challenges such as optical and EUV lithography, patterning technologies, metrology, and process integration for semiconductor manufacturing and adjacent applications are all covered. This… Read More
Unraveling Dose Reduction in Metal Oxide Resists via Post-Exposure Bake Environment
In the realm of extreme ultraviolet (EUV) lithography, metal oxide resists (MORs) have emerged as promising candidates for advanced semiconductor patterning. However, their stability poses challenges, particularly interactions with clean-room environments like humidity and airborne molecular contaminants (AMCs) … Read More
Agentic AI and the Future of Engineering
Agentic AI emerges in this Synopsys Converge keynote not as a futuristic add-on, but as a practical response to the growing complexity of engineering. In the speaker’s view, the traditional way of designing chips, systems, and intelligent products is no longer sufficient for the era of physical AI. Engineers are now dealing with… Read More
Ravi Subramanian on Trends that are Shaping AI at Synopsys
Right before the Synopsys Converge Keynote I caught an interview with Ravi Subramanian, Chief Product Management Officer at Synopsys, which highlights several important trends shaping the future of AI, semiconductor technology, and engineering. His discussion focuses on how the worlds of silicon design and system engineering… Read More
Qnity and Silicon Catalyst Light a Path to Success at the Chiplet Summit
The Chiplet Summit recently concluded. Multi-die heterogeneous design is a hot topic these days and chiplets are a key enabler for this trend. The conference was noticeably larger this year. There were many presentations and exhibits that focused on areas such as how to design chiplets, what standards are important, how to integrate… Read More
The Evolution of RISC-V and the Role of Andes Technology in Building a Global Ecosystem
During my frequent trips to Taiwan as a foundry relationship professional I remember meeting Frankwell Lin, CEO of Andes, in Taiwan 15+ years ago. As I walked to TSMC HQ from the Hotel Royal (my second home for many years) Andes was about mid point and Frankwell’s door was always open. Sometimes just tea, sometimes technology,… Read More
Keynote: On-Package Chiplet Innovations with UCIe
In the rapidly evolving landscape of semiconductor technology, the Universal Chiplet Interconnect Express (UCIe) emerges as a groundbreaking open standard designed to revolutionize on-package chiplet integrations. Presented by Dr. Debendra Das Sharma, Chair of the UCIe Consortium and Intel Senior Fellow, at the Chiplet… Read More
Perforce and Siemens Collaborate on 3DIC Design at the Chiplet Summit
The recent Chiplet Summit at the Santa Clara Convention Center was buzzing with many enabling technologies for chiplet-based design. Collaboration was also on display during many parts of the show. A presentation in the Siemens booth was a perfect example of both of those trends. In the Siemens booth, Perforce presented an excellent… Read More
Advancing Automotive Memory: Development of an 8nm 128Mb Embedded STT-MRAM with Sub-ppm Reliability
The rapid evolution of automotive technology has intensified the demand for highly reliable, high-performance semiconductor memory solutions. Modern vehicles increasingly rely ADAS driving features, and complex infotainment platforms, all of which require memory that can operate flawlessly under extreme environmental… Read More
Designing the Future: AI-Driven Multi-Die Innovation in the Era of Agentic Engineering
At the 2026 Chiplet Summit, Synopsys presented a bold vision for the future of semiconductor innovation: AI-driven multi-die design powered by agentic intelligence. As the semiconductor industry shifts rapidly toward chiplet-based architectures and 3D stacking, the complexity of design, verification, and system integration… Read More


Why Huawei Says It Will Match TSMC’s Most Advanced Chips by 2031