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Mentor Calibre Panel

Mentor Calibre Panel
by Alex Tan on 07-09-2018 at 12:00 pm

Getting your tape-out done on time is hard, but can it be made easier? That was the main topic of Mentor’s Calibre Panel held at DAC 2018, attended by a few key players in IC design ecosystem: Bob Stear, VP of Marketing at Samsung represented the foundry side; from the IP side, Prasad Subramaniam, VP of eSilicon for R&D and Technology;… Read More


55DAC Trip Report IP Quality

55DAC Trip Report IP Quality
by Daniel Nenni on 07-09-2018 at 7:00 am

This year I signed books in the Fractal booth (compliments of Fractal) and let me tell you it was quite an experience. IP quality is a very touchy subject and the source of many more tape-out delays than I had imagined. As it turns out, commercial IP is the biggest offender which makes no sense to me whatsoever. Even more shocking, one… Read More


Liberate Trio Embraces ML and Cloud

Liberate Trio Embraces ML and Cloud
by Alex Tan on 07-05-2018 at 12:00 pm

A chain is as strong as its weakest link. This phrase resonates well in Static Timing Analysis (STA) domain, though it is about accuracy rather than durability. As timing signoff step provides the final performance readings of a design, an STA outcome is as good as its underlying components. Aside from the parasitic extraction … Read More


55DAC Trip Report Needham Opening Presentation

55DAC Trip Report Needham Opening Presentation
by Daniel Nenni on 07-04-2018 at 7:00 am

Driving into DAC on Sunday afternoon was a chore since Gay Pride week was finishing with the Gay Pride Parade. Streets were closed, traffic was crazy, and people were roller skating naked which seems wrong on so many levels. This year the opening ceremonies were in the convention center hallway which also seemed wrong. Long lines… Read More


DAC 2018 Potpourri

DAC 2018 Potpourri
by Alex Tan on 07-03-2018 at 12:00 pm

The venue
Despite of being held at the new three-story Moscone West building, this year 55th DAC in San Francisco bore many similarities as compared with last year’s. Similar booth decors and floorplan positioning of the big two, Synopsys and Cadence, which were across of each other and right next to the first floor entrance –although… Read More


IITC – Imec Presents Copper, Cobalt and Ruthenium Interconnect Results

IITC – Imec Presents Copper, Cobalt and Ruthenium Interconnect Results
by Scotten Jones on 07-02-2018 at 12:00 pm

The IEEE Interconnect Technology Conference (IITC): Advanced Metallization Conference was held June 4th through 7th in Santa Clara. Imec presented multiple papers on comparing copper, cobalt and ruthenium interconnect. One paper in particular caught my eye: Marleen H. van der Veen, # N. Heylen, O. Varela Pedreira, S. Decoster,… Read More


55DAC Trip Report with Drama

55DAC Trip Report with Drama
by Daniel Nenni on 07-02-2018 at 7:00 am

This was my 35th DAC and it did not disappoint, especially when it came to the DAC Drama Department. This year DAC proved once again that it is THE place for semiconductor professionals and academics to learn and network. The big news is that Synopsys did not reserve a booth for 56DAC in Las Vegas next year which resulted in quite a bit… Read More


Design for Power: An Insider View

Design for Power: An Insider View
by Bernard Murphy on 06-28-2018 at 7:00 am

The second keynote at Mentor’s U2U this year was given by Hooman Moshar, VP of Engineering at Broadcom, on the always (these days) important topic of design for power. This is one of my favorite areas. I have, I think, a decent theoretical background in the topic, but I definitely need a periodic refresh on the ground reality from the… Read More


Imec technology forum 2018 – the future of scaling

Imec technology forum 2018 – the future of scaling
by Scotten Jones on 06-27-2018 at 12:00 pm

At the Imec technology forum in Belgium, Dan Mocuta and Juliana Radu presented “Evolution and Disruption: A Perspective on Logic Scaling and Beyond”, I also had a chance to sit down with Dan and discuss the presentation.

Device scaling

Scaling of devices will only get you so far, you need to look at new devices and new… Read More


RISC-V Ready (Tools) Set (Security) Go (Build)

RISC-V Ready (Tools) Set (Security) Go (Build)
by Camille Kokozaki on 06-26-2018 at 12:00 pm

The second Bay Area RISC-V Meetup event was held at the DoubleTree Hilton in Burlingame on June 19 with about 150 attendees. This event was hosted by SiFive and started with a networking session. The topics and speakers for the evening were:

  • Commercial Software Tools – Larry Lapides, Imperas
  • Securing RISC-V Processors
Read More