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The intricacies of analog IP circuit design have always required special consideration during physical layout. The need for optimum device and/or cell matching on critical circuit topologies necessitates unique layout styles. The complex lithographic design rules of current FinFET process nodes impose additional restrictions… Read More
We might wish that all our design automation needs could be handled by pre-packaged vendor tool features available at the push of a button, but that never was and never will be the case. In the language of crass commercialism, there may be no broad market for those features, even though you consider that analysis absolutely essential.… Read More
Synopsys hosted a lunch session on Thursday of DVCon. Michael Sanie of Synopsys opened the session, with a look back at the last DVCon where he had talked about Verification Compiler (VC) and extending the platform to Verification Continuum, which adds emulation and FPGA-based prototyping (HAPS – there was a very cool HAPS demo… Read More
EDAC hosted an event at DVCon this week where Jim Hogan interviewed Ajoy Bose (CEO of Atrenta prior to its acquisition by Synopsys). The nominal purpose was to talk about turning a venture into a valuable enterprise. This was covered but, in Jim’s way, it was really a more wide-ranging and personal interview. This is an abstract of… Read More
It’s that time of year again – DVCon starts on Monday Feb 29[SUP]th[/SUP] and as always should be a packed event. Synopsys plans a big showing, in the exhibit hall, in a sponsored lunch, at tutorials and in papers. Time to get your conference shoes on and go check them out – I plan to be there all week.
One of the most obvious things you will… Read More
When technology advances, complexities increase and data size becomes unmanageable. Fresh thinking and a new environment for automation are needed to provide the required increase in productivity. Specifically in case of circuit simulation of advanced-node analog designs, where precision is paramount and a large number… Read More
A maturetool. A legacytool. A tool that’s a little long in the tooth. We have all used these terms to refer to an EDA product that has not been able to keep up with technical challenges of model complexity, performance, or new features required by current SoC and system design requirements.… Read More
Clock domain crossing (CDC) analysis has been around for many years, initially as special checks in verification or static timing analysis, but it fairly quickly diverged into specialized tools focused just on this problem. CDC checks are important because (a) you can lose data or even lock up at, or downstream of a poorly-handled… Read More
Analog and mixed signal design has received more than their fair share of attention since the mobile revolution and now that FinFETs are in production at the foundries I see that trend continuing. As a result this year there are some interesting things brewing in EDA, especially in the area of Custom Layout.
Innovation in Custom … Read More
It has been almost five years since Marc Andreessen wrote the words, “Software is eating the world.” The premise of his essay in the Wall Street Journal in 2011 was pretty simple: the technology world has seen its intrinsic value shift from hardware to software. New all-software names have appeared on the list of high flying companies,… Read More
Podcasts
Podcast EP219: How Synopsys Addresses Debug and Coverage Closure Challenges with Robert Ruiz
Podcast EP188: The New Demands for Memory Design and the Synopsys Approach with Anand Thiruvengadam
Podcast EP185: DRAM Scaling, From Atoms to Circuits with Synopsys’ Dr. Victor Moroz
Podcast EP178: An Overview of Advanced Power Optimization at Synopsys with William Ruby
Podcast EP169: How Are the Standards for the Terabit Era Defined?
Podcast EP152: An Informal Conversation with Aart de Geus on AI and Multi-Die at SNUG
Podcast EP148: The Synopsys View of High-Performance Communication and the Role of Chiplets
Podcast EP141: The Role of Synopsys High-Speed SerDes for Future Ethernet Applications
Podcast EP240: Challenges and Strategies to Address New Embedded Memory Architectures with Mark Han
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