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Catching low-power simulation bugs earlier and faster

Catching low-power simulation bugs earlier and faster
by Daniel Payne on 08-15-2016 at 7:00 am

I’ve owned and used many generations of cell phones, starting back in the 1980’s with the Motorola DynaTAC phone and the biggest usability factor has always been the battery life, just how many hours of standby time will this phone provide and how many minutes of actual talk time before the battery needs to be recharged again. My smart phone today is the Samsung Galaxy Note 4, and I can make it through an entire business day before a recharge, so that’s real progress on usability for battery life.

Engineers love to model, simulate and predict the battery usage of consumer devices like our popular smart phones. At the other end of the power spectrum are electronic products like servers, where the cost to keep the racks cool contributes to the operating costs in a big way. What’s the best methodology to design and debug for low-power then?

Hardware designers have been using RTL coding for many years, so that’s a well understood methodology. UPF is being adopted more frequently now to define the power architecture, but how does that fit into an EDA tool flow exactly?

To learn more about catching low-power simulation bugs earlier and faster there’s a 60 minute webinar on August 31 from EDA vendor Synopsys. The specific EDA tool from Synopsys is called Verdi and the power-aware features will be introduced with an objective of:

[LIST=1]

  • How visualization of the power architecture can help identify power strategy and connectivity issues upfront
  • How to use annotated power intent on source code, schematics and waveforms to rapidly root-cause power-related errors back to UPF/RTL
  • How to debug unexpected design behavior such as Xs caused by incorrect power-up/down sequences etc

    ​The two people from Synopsys that are speaking at this webinar include Vaishnav Gorur and Archie Feng, members of the verification group.


    Vaishnav Gorur is currently Staff Product Marketing Manager for debug products in the Verification Group at Synopsys. He has more than a decade of experience in the semiconductor and EDA industry, with roles spanning IC Design, field applications, technical sales and marketing. Prior to joining Synopsys, Vaishnav worked at Silicon Graphics, MIPS Technologies and Real Intent. He has a Masters degree in Computer Engineering from University of Wisconsin, Madison and is currently pursuing an M.B.A. at University of California, Berkeley.

    Archie Feng is currently a Corporate Applications Engineer for debug products in the Verification Group at Synopsys. He has more than 15 years of experience in IC design and the EDA industry. Prior to joining Synopsys, Archie was an ASIC designer at the Industrial Technology Research Institute of Taiwan and has held positions in software design, applications engineering and product marketing at Springsoft. He has a Bachelors in Engineering Science from National Cheng-Kung University and a Masters in Computer Science from National Chung-Cheng University in Taiwan.

    REGISTER ONLINE

    This webinar is the 2nd of 4 planned on verification, you may watch the archived 1st webinar in the series:


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