Synopsys Tackles Debug for Giga-Runs on Giga-Designs

Synopsys Tackles Debug for Giga-Runs on Giga-Designs
by Bernard Murphy on 03-12-2019 at 12:00 pm

I think Synopsys would agree that they were not an early entrant to the emulation game, but once they really got moving, they’ve been working hard to catch up and even overtake in some areas. A recent webinar highlighted work they have been doing to overcome a common challenge in this area. Being able to boot a billion-gate design, … Read More


Quantifying Formal Coverage

Quantifying Formal Coverage
by Bernard Murphy on 05-03-2017 at 7:00 am

Verification coverage is a tricky concept. Ideally a definition would measure against how many paths were tested of every possible path through the complete state graph, but that goal is unimaginably out of reach for any typical design. Instead we fall back on proxies for completeness, like hitting every line in the code. This … Read More


Power-Aware Debug to Find Low-Power Simulation Bugs

Power-Aware Debug to Find Low-Power Simulation Bugs
by Daniel Payne on 09-09-2016 at 12:00 pm

When I worked at Intel designing custom chips my management would often ask me, “Will first silicon work?” My typical response was, “Yes, but only for the functions that we could afford to simulate before tape-out.” This snarky response would always cause a look of alarm, quickly followed by a second … Read More


Catching low-power simulation bugs earlier and faster

Catching low-power simulation bugs earlier and faster
by Daniel Payne on 08-15-2016 at 7:00 am

I’ve owned and used many generations of cell phones, starting back in the 1980’s with the Motorola DynaTAC phone and the biggest usability factor has always been the battery life, just how many hours of standby time will this phone provide and how many minutes of actual talk time before the battery needs to be recharged… Read More


Bringing Formal Verification into Mainstream

Bringing Formal Verification into Mainstream
by Pawan Fangaria on 04-28-2016 at 7:00 am

Formal verification can provide a large productivity gain in discovering, analyzing, and debugging complex problems buried deep in a design, which may be suspected but not clearly visible or identifiable by other verification methods. However, use of formal verification methods hasn’t been common due to its perceived complexity… Read More


VC Apps Tutorial at DVCon 2016

VC Apps Tutorial at DVCon 2016
by Bernard Murphy on 03-17-2016 at 7:00 am

We might wish that all our design automation needs could be handled by pre-packaged vendor tool Image Removedfeatures available at the push of a button, but that never was and never will be the case. In the language of crass commercialism, there may be no broad market for those features, even though you consider that analysis absolutely… Read More


Verdi Update and NVIDIA on Verification Compiler

Verdi Update and NVIDIA on Verification Compiler
by Bernard Murphy on 03-11-2016 at 12:00 pm

Synopsys hosted a lunch session on Thursday of DVCon. Michael Sanie of Synopsys opened the session, Image Removedwith a look back at the last DVCon where he had talked about Verification Compiler (VC) and extending the platform to Verification Continuum, which adds emulation and FPGA-based prototyping (HAPS – there was a very… Read More


Michael Sanie Plays the Synopsys Verification Variations

Michael Sanie Plays the Synopsys Verification Variations
by Paul McLellan on 08-31-2015 at 7:00 am

Image RemovedI met Michael Sanie last week. He is in charge of verification marketing at Synopsys. I know him well since he worked for me at both VLSI Technology and Cadence. In fact his first job out of college was to take over support of VLSIextract (our circuit extractor), which I had written. But we are getting ahead.

Michael was… Read More


End-to-end look at Synopsys ProtoCompiler

End-to-end look at Synopsys ProtoCompiler
by Don Dingee on 07-28-2014 at 9:00 pm

Usually, we get the incremental story in news: this new release is x percent better at this or that than the previous release, and so on. Often missing is the big picture, telling how the pieces all tie together. Synopsys took on that challenge in their latest FPGA-based prototyping webinar. … Read More


Hardware/Software Debug

Hardware/Software Debug
by Paul McLellan on 05-04-2014 at 10:59 pm

Image RemovedOne of the big challenges with modern SoCs is that they have a complex software component as well as the hardware itself being complex. Some aspects of the hardware can be debugged independently of the software and vice versa, but often it is not immediately clear whether the source of a problem is hardware, software… Read More