hip webinar automating integration workflow 800x100 (1)
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A Review of an Analog Layout Tool called HiPer DevGen

A Review of an Analog Layout Tool called HiPer DevGen
by Daniel Payne on 11-28-2011 at 1:11 pm

My last IC design at Intel was a Graphics Chip and I developed a layout generator for Programmable Logic Arrays (PLA) that automated the task, so I’ve always been interested in how to make IC layout more push-button and less polygon pushing. Today I watched a video about HiPer DevGen from Tanner EDA and wanted to share what I … Read More


December 1st – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC (Fremont, California)

December 1st – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC (Fremont, California)
by Daniel Payne on 11-24-2011 at 9:57 am

I’ve blogged about the Calibre family of IC design tools before:

Smart Fill replaced Dummy Fill Approach in a DFM Flow
DRC Wiki
Graphical DRC vs Text-based DRC
Getting Real time Calibre DRC Results with Custom IC Editing
Transistor-level Electrical Rule Checking
Who Needs a 3D Field Solver for IC Design?
Prevention is BetterRead More


How to use NoC to avoid routing congestion

How to use NoC to avoid routing congestion
by Eric Esteve on 11-23-2011 at 5:21 am

Network-on-Chip (NoC) is an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip. Sgroi et al. call “the layered-stack approach to the design of the on-chip intercore communications the Network-on-Chip (NOC) methodology.” In a NoC system, modules such as processorRead More


Reducing the Need for Guardbanding Flash ADC Designs

Reducing the Need for Guardbanding Flash ADC Designs
by SStalnaker on 11-22-2011 at 7:59 pm

Flash analog-to-digital converters (ADCs) are commonly used in high-frequency applications such as satellite communications, sampling oscilloscopes, and radar detection. Flash ADC is preferred over other ADC architectures because it is extremely fast and quite simple. However, flash ADC typically requires twice as many… Read More


David Liu, Kauffmann Award winner

David Liu, Kauffmann Award winner
by Paul McLellan on 11-22-2011 at 6:16 pm

David Liu receeived the Kaufman award for 2001 at the Kaufman award dinner a few weeks ago.

Or to be more formal about it:Dr. C. L. David Liu, the William Mong honorary chair professor of Computer Science and former president of the National Tsing Hua University in Hsinchu, Taiwan, will be presented with this year’s Phil Kaufman Award… Read More


Multi-Mode Simulation – What’s New at Cadence?

Multi-Mode Simulation – What’s New at Cadence?
by Daniel Payne on 11-21-2011 at 6:52 pm

Every week I receive several webinar invitations, so the recent one from Cadence about Virtuoso Multi-Mode simulation caught my fancy because I had met with John Pierce at DAC and wanted to see what was new since then and see how they compared with Mentor and Synopsys tools.


John Pierce, Product Marketing Director

This webinar runs… Read More


The Power of the Platform!

The Power of the Platform!
by Daniel Nenni on 11-16-2011 at 10:06 am

The Nintendo Wii is one of the most successful gaming platforms with the most diverse set of games — from fun games that can be enjoyed by the whole family to fitness programs that can be used by adults. They beat the dominant Sony Playstation and the Microsoft Xbox by thinking outside the box and creating a platform that was really… Read More


Formally verifying protocols

Formally verifying protocols
by Paul McLellan on 11-15-2011 at 1:19 pm

I attended much of the Jasper users’ group a week ago. There were several interesting presentations that I can’t just blog about because companies are shy, and some that would only be of interest if you were a user of Jasper’s products on a daily basis.

But for me the most interesting presentations were several… Read More


Physical Verification of 3D-IC Designs using TSVs

Physical Verification of 3D-IC Designs using TSVs
by Daniel Payne on 11-12-2011 at 10:36 am

3D-IC design has become a popular discussion topic in the past few years because of the integration benefits and potential cost savings, so I wanted to learn more about how the DRC and LVS flows were being adapted. My first stop was the Global Semiconductor Alliance web site where I found a presentation about how DRC and LVS flows were… Read More


EDA Interoperability Forum

EDA Interoperability Forum
by Paul McLellan on 11-09-2011 at 3:06 pm

The 24th Interoperability Forum is coming up at the end of the month on November 30th to be held at the Synopsys compus in Mountain View. It lasts from 9am until lunch (and yes, Virginia, there is such a thing as a free lunch). I think it looks like a very interesting way to spend a morning.

Here are the speakers and what they are speaking… Read More