TSMC announced today that together with ARM they have taped out the first ARM Cortex-A57 64-bit processor on TSMC’s 16nm FinFET technology. The two companies cooperated in the implementation from RTL to tape-out over six months using ARM physical IP, TSMC memory macros, and a commercial 16nm FinFET tool chain enabled by TSMC’s open innovation platform (OIP).
ARM announced the Cortex-A57 along with the new ARMv8 instruction architecture back at the end of October last year, along with the Cortex-A53 which is a low-power implementation. The two cores can be combined in the big.LITTLE configuration to combine high performance with power efficiency.
Since the beginning, ARM processors have been 32 bit, even back when many controllers in markets like mobile were 16 bit or even 8 bit. This is the first of the new era of 64-bit ARM processors. These are targeted at datacenters and cloud computing, and so is a much more head-on move into Intel’s core market. Of course, Intel is also trying, with Atom, to get into mobile where ARM remains the king. I doubt that this processor will be used in mobile for many years. There is a rule of thumb that what is used on the desktop migrates into mobile 5 years later.
TSMC have been working with ARM for several process nodes over many years. At 40nm they had optimized IP. Then at 28nm they taped out a 3GHz ARM Cortex-A9. At 20nm it was a multi-core Cortex-A15. Now, at 16nm, a Cortex-A57.
This semiconductor process is basically one with the power and drive advantages of FinFET transistors, but with the more mature 20nm metal fabric that does not require excessive double patterning and the attendant extra cost. This process is 2X the gate density of 28nm with 30+% speed improvement and power at least 50% less. This 16FF process enters risk-production at the end of this year. Everything needed for doing design from both TSMC and its ecosystem partners is available now for early adopters.
As I talked about last week when Cliff Hou of TSMC presented a keynote at SNUG, modern processes don’t allow all the development to be serialized. The process, the design tools and the IP needs to be developed in parallel. This test chip is a big step, since it is a tapeout of an advanced core very early in the life-cycle of the process. In addition to being a proof of concept it will offer opportunities to learn all the way through the design and manufacturing process.
Last year, TSMC had capacity to produce 15.1 million 8-inch equivalent wafers. If my calculation is correct that is over 1000 acres of silicon. That’s a pretty big farm.
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