If you’re in verification and you don’t know who Paul Cunningham is, this is a guy you need to have on your radar. Paul has risen through the Cadence ranks fast, first in synthesis and now running the verification group, responsible for about a third of Cadence revenue and a hefty percentage of verification tooling in the semiconductor… Read More
Lip-Bu Keynote at CDNLive 2019
Cadence CEO Lip-Bu Tan is always an interesting guy to listen to for his broader technology industry overview and his insight into emerging tech through his Walden International investments. Though we’re usually heads-down in challenging technical problems, it’s good to look up from time to time to check whether what … Read More
My Thoughts on Cadence in the Cloud
The cloud is a highly popular term that a lot of people don’t fully understand. If you are one of those people please read on as I will share my experience, observations, and opinions. Even if you are a cloud aficionado you may want to catch up on what’s new with EDA cloud services so again read on.
When we first started SemiWiki 9 years … Read More
Solving the EM Solver Problem
The need for full wave EM solvers has been creeping into digital design for some time. Higher operating frequencies – like those found in 112G links, lower noise margins – caused by multi level signaling such as in PAM-4, and increasing design complexity – as seen in RDL structures, interposers, advanced connector… Read More
Update on SystemC for High-Level Synthesis
The scope of current system designs continues to present challenges to verification and implementation engineering teams. The algorithmic complexity of image/voice processing applications needs a high-level language description for efficient representation. The development and testing of embedded firmware routines… Read More
A Smarter Way to Do Multi-Board PCB Systems
Many electronic product ideas start out as sketches on the back of a napkin, then migrate over to diagrams drawn in Visio or PowerPoint, finally entered into EDA-specific tools. With that methodology there’s a big disconnect between the diagrams drawn with a purely graphical tool and the EDA tools, because there’s… Read More
Intelligent Electronic Design Exploration with Large System Modeling and Analysis
At the recent DesignCon 2019 in Santa Clara, I attended a couple of sessions where Cadence and their research partners provided some insight on machine learning/AI and on large system design analysis; with the first one focused on real-world cloud & machine learning/AI deployment for hardware design and the second one focused… Read More
Project Verification Planning for Analog Designs
Successful projects leverage the investment in comprehensive methodology and resource planning, covering design and analysis flows – that planning effort is especially important for functional verification.
The emergence of complex SoC designs for advanced automotive applications has led to a major focus on verification… Read More
At Last, Package and Chip integration for RF Design
It seems that it has always been that there were packages and ICs, and in the design tool world “never the twain shall meet”. The tools for designing packages were completely separate from the tools used to design IC’s. This was so profoundly true that even after Cadence merged with Valid Logic back in the early 90’s, their Allegro … Read More
Cadence Automotive Summit Sensor Enablement Highlights
At the November 14 Cadence Automotive Summit, Ian Dennison, Senior Group Director, outlined sensor enablement technologies and SoC mixed-signal design solutions, from Virtuoso electrically aware design with high current, high reliability, yield and performance tools and methodologies enabling ADAS/AV sensors for vehicle… Read More