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WIKI Multi FPGA Design Partitioning 800x100 
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Aldec
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High Frequency Trading and EDA

High Frequency Trading and EDA
by Bernard Murphy on 05-16-2017 at 7:00 am
Categories: Aldec, EDA, FPGA

Pop quiz – name an event at which an EDA vendor would be unlikely to exhibit. How about The Trading Show in Chicago, later this month? That’s trading as in markets, high-frequency trading, blockchain and all that other trading-centric financial technology. This is another market, like cloud, where performance is everything and… Read More

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A Self-Contained Software-Driven Prototype

A Self-Contained Software-Driven Prototype
by Bernard Murphy on 04-26-2017 at 7:00 am
Categories: Aldec, Automotive, EDA, Prototyping, Xilinx

You’re building an IP, subsystem or SoC and you want to use a prototype together with a software testbench to drive extensive validation testing. I’m not talking here about the software running on the IP/SoC processor(s); the testbench should wrap around the whole DUT. This is a very common requirement. The standard approach to… Read More

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Aldec Swings for the Fences

Aldec Swings for the Fences
by Bernard Murphy on 03-17-2017 at 7:00 am
Categories: Aldec, Automotive, EDA, FPGA, IoT

In today’s fast-moving technology markets, companies who are prepared to step up to opportunity can break out of traditional bounds to become players in bigger and fast-growing markets. It looks to me like Aldec is putting itself on that path. They have announced an end-to-end hardware/software co-verification solution… Read More

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Aldec Rounds Out ALINT-PRO Checker

Aldec Rounds Out ALINT-PRO Checker
by Bernard Murphy on 02-16-2017 at 7:00 am
Categories: Aldec, EDA, FPGA

If there’s anyone out there who still doesn’t accept the importance of static RTL verification in the arsenal of functional verification methods, I haven’t met any recently. That wasn’t the case in my early days in this field. Back then I grew used to hearing “I don’t make mistakes in my RTL”, “I’ll catch that in simulation”, “My editor… Read More

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3 in 1 Hardware Verification

3 in 1 Hardware Verification
by Bernard Murphy on 11-14-2016 at 12:00 pm
Categories: Aldec, EDA, FPGA, Prototyping, Xilinx

Aldec has offered front-end EDA tools for over 30 years but may not be a familiar name to mainstream IC design engineers. That’s probably because for most that period they haven’t really targeted IC design. They have been much more focused on PC-based design for FPGAs particularly where requirements traceability has been important,… Read More

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FPGAs for a few thousand devices more

FPGAs for a few thousand devices more
by Don Dingee on 10-24-2016 at 4:00 pm
Categories: Aldec, Automotive, EDA, FPGA, IoT, Xilinx

An incredibly pervasive trend at last year’s ARM TechCon was the IoT, and I expect this year to bring even more of the same, but with a twist. Where last year was mostly focused on ultra-low power edge devices and the mbed ecosystem, this year is likely to show a better balance of ideas across all three IoT tiers. I also expect a slew of … Read More

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Case study illustrates 171x speed up using SCE-MI

Case study illustrates 171x speed up using SCE-MI
by Don Dingee on 10-12-2016 at 4:00 pm
Categories: Aldec, EDA

As SoC design size and complexity increases, simulation alone falls farther and farther behind, even with massive cloud farms of compute resources. Hardware acceleration of simulation is becoming a must-have for many teams, but means more than just providing emulation… Read More

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Up front phases improve CDC analysis

Up front phases improve CDC analysis
by Don Dingee on 09-19-2016 at 4:00 pm
Categories: Aldec, EDA, FPGA

Many tools find clock domain crossings (CDCs) in FPGA designs. Some don’t find the right ones since they don’t comprehend things like in-house synchronizer constructs. Some find too many based on misunderstanding intent, inaccurate constraints, and other factors that lead to noise.… Read More

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Optimization and verification wins in IoT designs

Optimization and verification wins in IoT designs
by Don Dingee on 08-17-2016 at 4:00 pm
Categories: Aldec, Automotive, EDA, FPGA, IoT, Xilinx

Designers tend to put tons of energy into pre-silicon verification of SoCs, with millions of dollars on the line if a piece of silicon fails due to a design flaw. Are programmable logic designers, particularly those working with an SoC such as the Xilinx Zynq, flirting with danger by not putting enough effort into verification?… Read More