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Next Generation Formal Technology to Boost Verification

Next Generation Formal Technology to Boost Verification
by Pawan Fangaria on 06-08-2015 at 12:00 pm

With growing complexities and sizes of SoCs, verification has become a key challenge for design closure. There isn’t a single methodology that can provide complete verification closure for an SoC. Moreover creation of verification environment including hardware, software, testbench and testcases requires significant … Read More


Logic Synthesis Reborn

Logic Synthesis Reborn
by Daniel Payne on 06-03-2015 at 9:45 am

Combine the pressures of Moore’s Law which enable billion transistor SoCs and the shortened time to market from consumer electronics product cycles and you have the perfect storm for EDA tool vendors. A modern SoC can have 500 or more blocks, creating both a design and verification challenge. How in the world do you write … Read More


Accelerate Modern PCB Design and Manufacturing

Accelerate Modern PCB Design and Manufacturing
by Pawan Fangaria on 05-24-2015 at 12:00 pm

In modern electronic industry PCBs are required to accommodate highly dense circuits with large number of components and complex routing spaces. While the complexity is increasing, the time-to-market is decreasing. In such a scenario, there is no other option than to reduce the design time by employing innovative editing options… Read More


Feed Your Mind and Body at 52nd DAC!

Feed Your Mind and Body at 52nd DAC!
by Daniel Nenni on 05-10-2015 at 4:00 am

My beautiful wife and I attend the Design Automation Conference together whenever possible. More so now that she is the co-founder and CFO of SemiWiki. It is really nice for her to put a face to the invoices and personally thank our subscribers. Her first DAC was 1985 in Las Vegas. We were married for less than a year so it was like a secondRead More


SoC Debugging Just Got a Speed Boost

SoC Debugging Just Got a Speed Boost
by Daniel Payne on 04-28-2015 at 4:00 am

Sure, design engineers can get more attention than verification engineers, but the greater number of verification engineers on SoC projects means that the verification task is a bigger bottleneck in a schedule than pure design work. A recent survey conducted at Cadence shows how verification effort can be divided into several,… Read More


Growing Innovation in Modern PCB Design Tools

Growing Innovation in Modern PCB Design Tools
by Pawan Fangaria on 04-26-2015 at 7:00 am

In last 30+ years, the electronic design industry has seen rapid changes more than any other industry. The change has taken place in the whole electronic ecosystem including semiconductor technology, transistor design, IC / SoC design, PCB, and system design. Today, a PCB can be very complex connecting several heterogeneous… Read More


Xtensa Fusion DSP Target IoT including Wireless and Security

Xtensa Fusion DSP Target IoT including Wireless and Security
by Eric Esteve on 04-23-2015 at 8:30 am

Internet of Things (IoT) can be seen as a fashionable buzzword covering so many distinct applications that IoT is sometimes nick-named “Internet of Everything”, or it can be perceived as the next revolution in electronic systems generating more revenues than the smartphone and computer market together in 2020. But the industry… Read More


ARM & Cadence IP Partnership for Faster SoC Design

ARM & Cadence IP Partnership for Faster SoC Design
by Eric Esteve on 03-18-2015 at 9:50 am

IP vendors always try to create differentiation, especially when designing protocol based IP. You can differentiate by building the most performing controller but you will probably miss the expectation of these customers who don’t search for performance but just compliance to a specific standard. Or the vendor may want to design… Read More


Cadence’s New Implementation System Promises Better TAT and PPA

Cadence’s New Implementation System Promises Better TAT and PPA
by Tom Simon on 03-12-2015 at 1:00 am

On Tuesday Cadence made a big announcement about their new physical implementation offering, Innovus, during the keynote address at the CDNLive event in Silicon Valley. Cadence CEO Lip-Bu Tan alluded to it during his kick off talk, and next up Anirudh Devgan, Senior Vice President, Digital & Signoff Group, filled in more … Read More


Innovus: Cadence’s Next Generation Implementation System

Innovus: Cadence’s Next Generation Implementation System
by Paul McLellan on 03-11-2015 at 7:00 am

Yesterday was the first day of CDNLive. There were three keynotes. The first was by Lip-Bu Tan, Cadence’s CEO (and the Chairman of Walden International that he will be the first to remind you). The most interesting tidbit was that Cadence now has over 1000 people working on IP and that it represents 11% of their revenue. Then… Read More