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Verification of Wireless RFIC Designs

Verification of Wireless RFIC Designs
by Daniel Payne on 01-15-2015 at 1:30 pm

Wireless technology is all around as I use cellular on an Android phone, WiFi to connect my MacBook Pro to the internet, Bluetooth for a headset, ANT+ for my cycling computer, and NFC to speed up electronic payments on the Android phone. Here’s a big picture look at some of the modern wireless standards available to choose from:

On the design side you choose which standard to implement, create block diagrams, add models to each block, then start the verification process to see if you’ve implemented the standard correctly. Co-simulation is one approach used in RFIC verification where an envelope simulator is connected to a wireless system simulator:

For verifying the IEEE 802.11 standard (WiFi) you would need to understand the documentation, then extract the needed frequency values:

  • Fundamental frequency
  • Step period
  • Frequency of resolution

Next up is manually configuring and controlling the simulation. On the wireless simulator you would generate an input, simulate one period of the carrier, go to a later time and then repeat the process. To evaluate a period the simulator could use the transistor-level (standard envelope) and run harmonic balance analysis at each time interval, although that is limited to just small RF modules and not for an entire RFIC.

Another approach is to characterize the circuit before the first period, write a behavioral model and then simulate the behavioral model through each time interval. Benefits of this behavioral model approach is a much faster simulation speed which then enables the entire RFIC to be simulated. Engineers at Cadence propose improving RFIC verification by following three steps:

[LIST=1]

  • An accurate characterization and modeling of the RF design
  • Use wireless standard-compliant modulation sources
  • Apply automation for system-level performance: Error Vector Magnitude (EVM), spectrum, Adjacent Channel Power Ratio (ACPR) and Bit Error Rate (BER) measurements

    Related – Cadence Mixed Signal Technology Forum

    This methodology uses one design environment along with a single kernel simulation engine, shown below:

    Designers would characterize each circuit using large signal analysis (harmonic balance). Next, a behavioral model is built. Now the time evaluations are started. The behavioral model is run to evaluate the circuit for each time interval, which produces quicker results than running a complete harmonic balance analysis for each interval.

    Cadence EDA Tools

    The design capture tool for Cadence is called Virtuoso Analog Design Environment, and the simulator is Spectre RF. You can use standards-based stimulus, saving verification time: IEEE 802.11 family, LTE, LTE-A, ZigBee and 802.15.4g. Modulated sources are found as components in a library, and they are used as input to the Design Under Test (DUT), making your simulation setup time a lot quicker.

    Related – How ST Designs with Layout Dependent Effects (LDE)

    In the GUI you select the wireless modulated source from a library, then the simulation engine automatically fills in the parameters: sampling rates, stop times, strobe options and carrier frequencies to comply with the standards.

    In Spectre RF the fast envelope simulation engine can characterize and then create a model of the DUT, giving you up to 1,000X faster simulation results compared to a transistor-level envelope simulation approach. RFIC architects and designers can see plots with constellation and ACPR, the critical measures of distortion:

    Summary

    RFIC designers and architects have choices when it comes to their design and verification methodology. The approach offered from Cadence has useful automation to reduce verification times in a single-vendor flow. View the complete 6 page white paper here for more details.

    Related – What’s New with Circuit Simulation for Cadence at DAC


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