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Ceaseless Field Test for Safety Critical Devices

Ceaseless Field Test for Safety Critical Devices
by Pawan Fangaria on 06-03-2014 at 3:00 am

While focus of the semiconductor industry has shifted to DACin this week and unfortunately I couldn’t attend due to some of my management exams, in my spare time I was browsing through some of the webpages of Cadenceto check their new offerings (although they have a great list of items to showcase at DAC) and to my pleasure I came across… Read More


Cadence Go (war-game) strategy

Cadence Go (war-game) strategy
by Eric Esteve on 05-26-2014 at 8:19 am

I was attending to CDN-Live in Munich last week, so I was expecting Cadence to announce new IP related acquisition like Lip-Bu Tan did last year (Cosmic Circuit, Evatronix and Tensilica). In fact, Lip-Bu was not in Munich and Charlie Huang, SVP Worldwide Field Operations and System & Verification Group, was holding the morning… Read More


A Collaborative Approach Yields Better PI for PCBs

A Collaborative Approach Yields Better PI for PCBs
by Pawan Fangaria on 05-18-2014 at 10:30 am

The power integrity (PI) of a system is an extremely important aspect to be looked at all levels – chip, package and PCB for overall reliability of the system. At the PCB level, a DC analysis, usually based on IR drop, must ensure that adequate DC voltage, satisfying all constraints of current density and temperature, is delivered… Read More


Panel: Strategies for Next Generation Semiconductor IP Management

Panel: Strategies for Next Generation Semiconductor IP Management
by Holly Stump on 05-16-2014 at 7:00 am

I just returned from the “Semiconductor Executive Briefing: Strategies for Next Generation Semiconductor IP Management” panel,held at the Computer History Museum, sponsored by Dassault Systèmes.

(Left to right) Moderator: Warren Savage, President and CEO, IPextreme, with panelists John Tam, Director of Business Development,Read More


Cadence @ #51DAC Must See!

Cadence @ #51DAC Must See!
by Daniel Nenni on 05-13-2014 at 3:00 pm

Cadence is excited to bring a full slate of demos, technical presentations, papers, and more to the Design Automation Conference (DAC) June 1-5, 2014, in San Francisco, CA. From our technical experts, you’ll learn tips and techniques from areas including low power, mixed signal, advanced nodes, signoff, verification, and IP,… Read More


Intel is Still Missing Mobile!

Intel is Still Missing Mobile!
by Daniel Nenni on 05-07-2014 at 9:00 am

Paul McLellan was on assignment in Hong Kong last week so I attended the Linley Mobile Conference and was not surprised Intel did not present. During the networking sessions I asked more than a dozen people why and the answers were pretty focused on “Intel still does not play well with others” and “Intel’s current mobile offerings… Read More


Eric Esteve to Present during CDN Live 2014 in Munich

Eric Esteve to Present during CDN Live 2014 in Munich
by Eric Esteve on 05-01-2014 at 4:00 am

I will have the privilege to give an “IP Outlook” presentation during next Cadence event in Europe, CDN-Live to be held in Munich the 19[SUP]th[/SUP] to 21[SUP]st[/SUP] of May. I had a look at the agenda, and the conference will be pretty busy, especially on Tuesday, as there will be more than fifty presentations, starting at 10:30… Read More


Cadence Acquires Jasper

Cadence Acquires Jasper
by Paul McLellan on 04-21-2014 at 4:06 pm

Cadence announced today that it is acquiring Jasper Design Automation for $170M in an all-cash offer. Jasper has $24M in cash so it is really an acquisition for around $145M. i think that is around 4X revenue but I only know rumors about Jasper’s revenue numbers.

All the big 3 already have their own formal technology but the … Read More


Signoff Accurate Timing Analysis at Improved Run-time & Capacity

Signoff Accurate Timing Analysis at Improved Run-time & Capacity
by Pawan Fangaria on 04-18-2014 at 4:30 pm

The semiconductor design sizes, these days, can easily be of the order of several hundred millions of cells, adding into the complexity of verification. Amid ever growing design sizes, it’s a must that the timing verification is done accurately. Normally Static Timing Analysis (STA) is done to check whether all clocks and signals… Read More


Does Processor IP still get the Lion’s share in 2013?

Does Processor IP still get the Lion’s share in 2013?
by Eric Esteve on 04-17-2014 at 1:00 pm

I think that the answer is pretty obvious, but the interesting point is to figure out which processor type, and which part of revenues, up-front license or royalties? One of my customers, let’s call him Mr. X, ask me to clarify this point. Mr. X has bought the excellent report from Gartner “Market Share: Semiconductor Design Intellectual… Read More