Digital @ Nano-Scale while Analog Hovers @ 65nm and Above

Who’s going to DesignCon next week? I am, absolutely. Dr. Hermann Eul, Vice President & General Manager, Mobile & Communications Group, Intel Corporation will be keynoting on Tuesday. This one I want to hear! Intel missed mobile at 32nm, 22nm, and 14nm. Lets see what they have planned for 10nm. Something good I hope!

Want to meet me? I will be on a panel in the Overcome Analog and Mixed-Signal Design and Verification Challengessession. Here is the abstract:

There’s a growing schism in the world of mixed-signal IC design. This stems from the increasing rate and pace of digital designs being created at deeper nano-scale process nodes while analog designs continue to hover at process nodes of 65, 90 and larger. Requirements both technological and business/market have a large influence on this division. Digital designers are under intense pressure to increase functionality and reduce cost , which drives higher chip density and reduced chip footprint. In contrast, analog requirements may call for high voltages or advanced RF capabilities that necessitate the larger process nodes. This all converges at the foundry where designs are transposed to silicon. How are foundries and EDA vendors addressing and/or overcoming this challenge? What design types and application areas are most likely to have to navigate this divide? How are design kits (PDKs) and other design enablers helping to mitigate the issue?

The Great Divide: Digital @ Nano-Scale while Analog Hovers @ 65nm and Above
Zhimin Ding | Anitoa Systems
Jeff Miller | Product Manager, Tanner EDA
Dan Nenni | Founder, SemiWiki.com
Mahesh Tirupattur | Executive Vice President, Analog Bits, Inc
John Zuk | VP Marketing & Business Strategy, Tanner EDA

Session Code: 2-WE7
Location: Ballroom E
Date: Wednesday, January 29
Time: 3:45pm-5:00pm

Session attendees will engage with experts from A/MS foundries & EDA tool vendors to discuss the growing divide between digital and analog design. Digital designs are racing down the process node path with current tape-outs at 20nm and roadmaps to 14 and 10nm. Mainstream analog and mixed-signal designs continue to tape out at 90, 180nm and above. Here, the long-term implications of this schism will be discussed.

Created by engineers for engineers, DesignConis the largest gathering of chip, board and systems designers in the world and is focused on the pervasive nature of signal integrity at all levels of electronic design – chip, package, board and system. Combining technical paper sessions, tutorials, industry panels, product demos and exhibits, DesignCon brings engineers the latest theories, methodologies, techniques, applications and demonstrations on PCB design tools, power and signal integrity, jitter and crosstalk, high-speed serial design, test & measurement tools, parallel & memory interface design, ICs, semiconductor components and more.

DesignCon enables chip, board and systems designers, software developers and silicon manufacturers to grow their design expertise, learn about and see the latest advanced design technologies & tools from top vendors in the industry, and network with fellow engineers and design engineering experts.

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