WP_Term Object
(
    [term_id] => 72
    [name] => STMicroelectronics
    [slug] => stmicroelectronics
    [term_group] => 0
    [term_taxonomy_id] => 72
    [taxonomy] => category
    [description] => 
    [parent] => 14433
    [count] => 77
    [filter] => raw
    [cat_ID] => 72
    [category_count] => 77
    [category_description] => 
    [cat_name] => STMicroelectronics
    [category_nicename] => stmicroelectronics
    [category_parent] => 14433
    [is_post] => 1
)

The Technology to Continue Moore’s Law…

The Technology to Continue Moore’s Law…
by Eric Esteve on 03-17-2014 at 11:59 am

Can we agree about the fact that the Moore’s law is discontinuing after 28nm technology node? This does not mean that the development of new Silicon technology, like 14nm or beyond, or/and new Transistor architecture like FinFET will not happen. There will be a market demand for chips developed on such advanced technologies: mobile applications or high performance computing to name a few. These applications exist, where more IP (multiples CPU, GPU, SRAM and various “functions”) have to be integrated into a single SoC, running faster than the previous generation but with a better power efficiency. But, when you add to this specification that a single SoC (platform) will have to ship by several dozen of million units, if not hundred, to fit with economics requirements, you realize that only a few applications will be concerned, not the majority. We have seen in a previous blog that the entry ticket for 14nm FinFET was close to $200 million (International Business Strategies, Inc. 2013 report). When you take a look at the picture below, you realize that the Manufacturing Fabs CAPEX (normalized to 1K Wafer per week) has increased by 86% from 28nm planar to 14nm FF. Going further in technology is possible, and will happen, but no more according with Moore’s law. We may even mention the last node marking Moore’s law limit, it’s 28nm!

So, what will happen to the mainstream semiconductor industry, in order to benefit from Moore’s law similar dynamic, if targeting smaller technology node is no more the solution, as it was for now the last 50 years? Our industry will have to be smart! We could say smarter than Moore!

There are certainly solutions, and most probably more than one track to explore. Smart packaging can be a way to increase density (board density instead of chip density), if you place side by side (2D) or pile up (3D), also lowering power dissipation, as the chip to chip interconnections will be shorter and far less capacitive inside the package, thus C*V[SUP]2[/SUP] will decrease. Another approach, directly linked with Silicon processing, can make sense: targeting Fully Depleted Silicon On Insulator (FD-SOI) technology. If you take a look at the above table, you can see that blindly following Moore’s law from 28 bulk, to 20nm bulk and 14nm FF lead to a performance improvement but also a cost increase. The reasons are process related, as we can see on the next picture:

The Bulk transistor architecture that we are using for decades is reaching limits at 20nm. These limits are linked with the law of physics, and lead to the following issues:

  • Transistor Channel Level: High Cost process flow and more critical process steps (impacting yield, then cost too)
  • Heavily Doped Wells (left of source, right of drain): High variability, forcing to a longer minimum gate length and severe layout limitations (impact on density, design becoming more and more complex to handle)
  • high leakage current: this one is a severe limitation, as it can annihilate the benefit gained on dynamic current improvement
  • Weak process compensation: in fact, the design/process co-optimization is low; we will see that Forward Body Bias effect in FD-SOI is a very smart way to compensate the process related variations, which exists whichever the technology.

Then, we can clearly see two possible routes. The closer to the previously known as Moore’s law is to design a FinFET transistor architecture, and to move one technology node further, leading to 14nm FF (apparently 20nm will not be used for long). We will see on the next picture the cost impact of this 3D technology. The other route is to manipulate the Silicon substrate and create a thin buried oxide, the FD-SOI technology, and stay with 2D (planar) architecture, moreover, stay with 28nm gate length!

If you compare the number of mask layers, and even more important the number of critical layers, 14nm exhibits 66% more critical layers than 28nm. Not a surprise, 14nm FF process will cost 38% more than 28nm. This is the right time to remind that SOI wafer cost is $500 higher than regular wafers. If you want to make a complete cost analysis, you also have to remind the 86% CAPEX increase to build the wafer fab! If you remember the wafer cost analysis published a while ago, CAPEX is a pretty heavy part of a processed wafer cost. If you multiply CAPEX by 1.86, that means that you will have to sell 86% more 14nm FF wafers than 28nm FDSOI to compensate this over CAPEX! Or you just say that 14nm FF is more expensive than 28nm FDSOI…

Thus, can we already say that FD-SOI is smarter than Moore?

Let’s take a look at these few examples: (1) CPU, GPU and Logic, (2) Memories and (3) Analog & High-speed, and try to analyze the FD-SOI benefits in respect with 28nm Bulk.

  • CPU, GPU and Logic: here we search for high performance, and power efficiency. FD-SOI technology exhibits excellent leakage power behavior (in fact, there is no source to bulk or drain to bulk leakage!), and the dynamic power can be lower by 30% (at equivalent performance, as described here), we can tick the power benefit. Performance: we have written about this high speed data networking ASIC, designed by a chip maker claiming for a 30% performance improvement, thanks to the Forward Body Bias effect. By the way, you can benefit from one of these 30% at the same time, or decide to optimize for the best performance to power efficiency, for a mobile application for example…
  • Memories: again the Silicon On Insulator technology direct benefit is the lower leakage compared to bulk, thus a SoC designer may optimize the architecture of an embedded IC, integrating more memory or designing for lower power.
  • Analog & High-speed: almost any SoC will integrate Analog (ADC or DAC) or High-speed PHY to support interface protocols (DDRn, USB 3.0, PCIe etc.). Paul has shown in this blog that FD-SOI analog performance is far beyond bulk one. This is going with a better figure of merit for high-speed IP.

So, can we say that a technology that exhibits lower cost than Bulk HPM & FinFET, a better reliability and yield, thanks to true process compensation through body bias and flexibility of usage is smarter than Moore? I would guess so…

From Eric Esteve from IPNEST

More Articles by Eric Esteve…..

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