WP_Term Object
    [term_id] => 72
    [name] => STMicroelectronics
    [slug] => stmicroelectronics
    [term_group] => 0
    [term_taxonomy_id] => 72
    [taxonomy] => category
    [description] => 
    [parent] => 14433
    [count] => 77
    [filter] => raw
    [cat_ID] => 72
    [category_count] => 77
    [category_description] => 
    [cat_name] => STMicroelectronics
    [category_nicename] => stmicroelectronics
    [category_parent] => 14433

FD-SOI Memories

FD-SOI Memories
by Paul McLellan on 01-08-2014 at 11:00 am

 When people discuss capabilities of leading edge process nodes they tend to focus on digital logic. Microprocessors in particular. But a process requires more than just digital logic and standard cells to be successful. In particular, pretty much every SoC contains a lot of memory so the memory capabilities of a process are important.

ST Microelectronics’s FD-SOI turns out to have a lot of big advantages over traditional planar for memories. A lot of this is due to the much lower leakage which has a number of knock-on effects.

Firstly, the minimum voltage required for the memory is much lower due to better mismatch on FD-SOI devices compared to planar, around 0.6V versus 0.7V. At 28nm, FD-SOI has a gain in leakage of 8X with the same performance.

But the biggest difference is in the reliability area and the sensitivity to neutrons and alpha particles. In 28nm FD-SOI the soft error rate (SER) for an SRAM is <10 FIT/Mb, which is 100X better than its bulk counterpart. This is so good that error correcting (ECC) is not systematically required for all memories as is pretty much required in large bulk SRAMs. Obviously this results in power and area savings.

The is also effectively immunity to alpha particle upsets which in turn means cost savings in packaging (which is the source of alpha particles since they won’t penetrate the packaging from outside, so only internally generated particles cause problems).

Since the error clusters are 99% single bit problems, when ECC is added then it only needs to correct single bit errors and there is no need to bit scrambling as there is with ECC in bulk processes.

For TCAM (ternary content addressable memory) where ECC is not usable this is a true differentiator. For example, you can build a 100Mb memory unmitigated TCAM while still offering <1000 FIT.

Another advantage of FD-SOI is its capability to operate at ultra-low voltage (ULV) around 0.25V-0.3V. One of the challenges at low voltage is that variability in the process causes problems. FD-SOI reduces this by a factor of 10. The performance is still 100s of MHz at 0.3V. This is important for internet of things (IoT), medical and other extreme low power applications. ST has a ULV design enablement kit available. Early in 2014 ST will have ULV ARM Cortex M4 and a SPARC ULV microprocessor too. Along with ULV memories this allows ULV SoCs to be built for markets that require extremely long operation time off small batteries.

More articles by Paul McLellan…

Share this post via:


There are no comments yet.

You must register or log in to view/post comments.