Word association: if I said “requirements management”, you’d probably say IBM Rational “DOORS,” or maybe Serena or Polarion if you come from the IT world. But what if the requirements you need to manage are for an FPGA or ASIC, with HDL and testbench code and waveform files and more details backing verification, and compliance to safety-critical standards is needed?
Continue reading “It’s all in the details of FPGA requirements management”
NanGate got started in 2004 by a group of engineers from Vitesse Semi and Intel. The technology and market idea was to address and solve the inherent shortcomings of standard cell based design as compared to full custom. Anyone having tried to push the performance of a standard cell design knows the frustration… if only I had a better library or if I could just have these extra cells made!
Standard cell libraries have been around for a long time and have grown in size and complexity from a few hundred cells to several thousand cells. The library design and the choice of which cells to have in the library are key factors to getting the most performance out of the technology and at the lowest power and area possible. The problem is that making a standard cell library takes a lot of effort and has to be a compromise between the power, performance, and area demands from different applications.
NanGate is about creating and optimizing standard cell libraries. They focus on automating the whole process from library specification to GDSII and Liberty. They support and generate all the views and formats needed to use the libraries with standard synthesis and place-and-route flows. Automation and high productivity are key. As the only library optimization company in the world they can generate layout in geometries from 14nm to 350nm from Boolean equations, SPICE netlists or stick diagrams and automatically find the optimal implementation in the selected technology and cell template. Nangate even supports GDSII-to-GDSII migration and DFM optimization.
The Nangat tool suite includes library characterization and library validation. As in digital design formal verification, STA and DRC are must-haves for any contemporary design flow. Validating the library characterization is just as important as any mistakes or modeling inaccuracies will have wide ranging consequences. The same is the case for validating the many different views in the library such as LEF and verilog.
NanGate’s tool suite has been developed, improved and proven in combat during the last 8 years. It required more than $25 million in venture capital funding and an engineering team of more than 30 engineers at the top to pull it off. By 2009, NanGate had 5 EDA products in the market for Library Creation, Characterization and Validation:
The products have been adopted by more than 15 customers and several public testimonials have been made by leading foundries and semiconductor companies such as TSMC, Fujitsu and Renesas. NanGate’s library platform has enabled customers to create custom libraries with much less effort and to push the performance higher.
As with the EDA industry in general, the VCs left Nangate in 2012 which enabled a management buyout. Today, Nangate Inc is fully owned and controlled by management. They have refocused the company on the core customers and competencies of NanGate. And probably most importantly, they have restructured the company to be Silicon Valley-based and profitable. Moving forward, NanGate will focus on library automation and optimization for the most advanced process nodes. Partnerships are key to NanGate’s future strategy; recently they integrated Sagantec’s 2D compaction engine to add a DRC correct clean-up step at the end of the layout generation flow. This complements the existing layout creation solution and enables the most powerful 14nm solution in the market today.
NanGate, a provider of physical intellectual property(IP) and a leader in Electronic Design Automation (EDA) software, offers tools and services for creation and validation of physical library IP, and analysis and optimization of digital design. NanGate’s suite of solutions includes Library Creator™ Platform, Design Optimizer™ and design services. NanGate’s solution enables IC designers to improve performance and power by concurrently optimizing design and libraries. The solution, which complements existing design flows, delivers results that previously could only be achieved with resource intensive custom design techniques.
DAC 2013 is closing in fast now…and if you haven’t made your plans for what you want to see and do, you’d better get going! Of course, I’m happy to help you out with a few suggestions…starting with that most important objective—conference swag. Stop by the Mentor Graphics booth (#2046, for those of you who actually look at your floor maps) any time Monday through Wednesday to pick up your plush Congress Bridge bat. And if you get the chance, go out one night and watch the real thing (take your camera!).
For those who like a bit of anticipation, we also have daily drawings. Prizes this year include an Apple iPad[SUP]®[/SUP]Mini, a Nintendo Wii U™, and a GoPro[SUP]®[/SUP]camera. You get an entry for every Mentor suite session you attend, and drawings will be held every day at our Happy Hour open bar, which starts at 4:00 pm. You don’t have to be present to win, but you must pick up your prize in person before the close of DAC.
If a lively bit of discussion is your thing, Mentor is participating in or hosting a number of panels at DAC. Join us for any or all. No advance registration is required.
Achieving IC Reliability in High Growth Markets
Monday, June 3, 3:00-4:00 (Mentor Booth #2046)
Will Data Explosion Blow Up the Design Flow?
Monday, June 3, 3:15-4:00 (DAC Pavilion Panel, Booth #509)
Advanced Node Reliability: Are We in Trouble?
Tuesday, June 4, 10:30-12:00 (DAC Technical Panel, Room 16AB) requires full conference access
Marrying More than Moore
Tuesday, June 4, 3:00-4:00 (Mentor Booth #2046)
No Fear of FinFET
Wednesday, June 5, 3:00-4:00 (Mentor Booth #2046)
It’s also worth noting that the Mentor Booth panels are followed immediately by the Mentor Happy Hour—great chance to mingle with like minds, while enjoying an adult beverage!
As for those suite sessions—as usual, we’ll be hosting a variety of presentations at the Mentor booth. Below are just a few that might appeal to the Design to Silicon crowd, but you can check out the full list any time. Registration is required to attend a suite session—click on the session title to get to our registration page.
Reliability Checks for Multiple Markets(Presented in Mandarin)
Monday, June 3, 10:00-11:00, Mentor booth #2046
你說中文嗎? 你说中文吗? Calibre PERC provides a fully automated and comprehensive EDA design platform to check ESD, latch-up, EOS, ERC and other design issues in both design and stream out databases. In this session, presented in Mandarin, Mentor Graphics and SMIC discuss reliability checking with Calibre PERC. Want to hear it in English? Sign up for one of the Comprehensive Circuit Reliability with Calibre PERC sessions (Monday, 2:00 or Wednesday, 10:00) in the Mentor booth.
Best Practices for 20nm Design
Monday, June 3, 2:00-3:00, Mentor booth #2046
If you’re planning or contemplating a move to 20nm, you need to be in the seats for this session. TSMC and Mentor present best practices learned from their experience helping leading-edge customers with the transition to 20nm. This vital knowledge will help you smoothly tapeout your designs for TSMC’s advanced processes.
Advancing Circuit Reliability at TowerJazz with Calibre PERC Rule Decks
Tuesday, June 4, 2:00-3:00, Mentor booth #2046
Intended for advanced Calibre users, this presentation demonstrates how TowerJazz uses Calibre PERC rule decks and the Calibre PERC product’s unique ability to combine schematic (netlist) and physical layout information to perform circuit reliability verification during signoff. ONE TIME ONLY, LIMITED SEATING.
Preparing for Pervasive Photonics
Tuesday, June 4, 2:00-3:00, Mentor booth #2046
Silicon photonics is coming—are you ready? This session discusses the impact photonics will have on today’s IC design and manufacturing processes, the tool requirements for SP, foundry options, new applications that SP will open up, and new challenges it will present to IC designers.
Of course, we won’t just be hanging out at the Mentor booth the whole time. Calibre experts will be speaking at our partners’ booths as well. We have a full list of partner activities, but here’s one technical presentation you won’t want to miss:
Identifying Critical Design Features from Silicon Results
Tuesday, June 4, 10:00-11:00, GLOBALFOUNDRIES Booth #1314
Ken Amstutz (Senior Application Engineer) will be talking about the collaboration between Mentor Graphics and GLOBALFOUNDRIES to rapidly identify systematic defects and critical design features based on silicon data. Layout-aware diagnosis identifies the location and classification of defects causing manufacturing test failures. Specialized statistical analysis coupled with design profiling data (such as critical feature analysis) then determines the root cause of yield loss and separates design- and process-induced defects. LIMITED SEATING – REGISTRATION REQUIRED
For a full round-up of Mentor activities at DAC, and to register for any of our suite sessions in advance, you can check us out at Mentor@DAC 2013. See you in Austin!!
I have mentioned NoC adoption explosion during the last two years, illustrated by the huge revenue growth of Arteris. This trend is now confirmed in the fastest moving segments, the Application Processors (AP) and LTE Modem for mobile applications. In fact, Arteris FlexNoC has been integrated in the majority of AP and LTE Modem chips being shipped in 2012 and shipping in 2013. What is the common and key feature for these chips?
Each of these is shipping by dozen of millions, all of them are extremely complex, counting 100 IP or more, and the Time To Market (TTM) is dramatically important: if a chip maker miss the release to production by only one months, several dozen if not hundred $ millions of chip sales just vanishes… and will never be catch-up, because OEM integrating these IC like Apple, Samsung or HTC have to release a new product generation almost every 6 months. If you take a look at the business won by Arteris since 2008, you will name most of the major semiconductor companies (even if you are not supposed to know the name of “Unannounced Customer”, just think about “Major”…).
If you come back to one of my very first post about Network on Chip, you remember that one of the most important NoC advantage is to avoid routing congestion on large SoC, thus accelerating TTM as the back-end cycles (Place and Route/post routing simulation/modification) are extremely time consuming. But we know that for IC like AP and LTE Modem, the key sales message will be about Performance, measured in term of main CPU Frequency, and Low Power, as these will be the most visible feature for the end user: can I use my smartphone right after opening it? Do I need to plug it every two hours or could I use it for days before charging? Arteris’ FlexNoC is also addressing these two very important requirements that every chip maker has… or that the company should have, in order to be successful!
It’s very interesting to see that the very fast growing chip makers or ASIC companies are also adopting the NoC, and the reasons why they adopt Arteris’ FlexNoC: high frequency, low gate count, lower power, higher flexibility or Quality of Service (QoS) are the most frequently mentioned advantages.
Fuzhou Rockchip Electronics Co. Ltd.
“Arteris FlexNoC interconnect IP enables us to exceed our design frequency and power requirements while giving us more flexibility than possible using older interconnect technologies, like buses and crossbars,” said Li Shiqin, IC Design Manager at Rockchip.
MegaChips Corporation
“From our experience with Arteris’ NoC technology over the years, we knew that Arteris FlexNoC IP was the fastest interconnect fabric for SoCs with multiple initiator and target IP blocks. However, we were surprised that FlexNoC could continue to run at fast design frequencies with a significantly lower gate count and less power consumption than alternative bus fabrics,” said Gen Sasaki, General Manager of Division No.2, MegaChips Corporation.
Open-Silicon, Inc.
“Arteris’ network-on-chip interconnect IP made timing closure much easier and allowed us to implement the QoS management required for the design’s high-performance I/O and sophisticated hardware acceleration engines. In addition, we were able to close timing in a fraction of the schedule needed previously for designs using older crossbar-based architectures,” said Colin Baldwin, senior director of marketing, Open-Silicon
When you see such a customer list, you understand why the company is claiming that FlexNoC is integrated into about 60% of the Application Processor and LTE Modem IC. When you know the associated shipments in smartphones and media tablet applications, you can guess that Arteris royalty revenues will sky rocket in 2013 and after!
To learn a lot more about NoC and Arteris products, just go here.
By Eric Esteve from IPNEST
As we get down to smaller and smaller process nodes, the problem of soft errors becomes increasingly important. These soft errors are caused by neutrons from cosmic rays, alpha particles from materials used in manufacture and other sources. For chips that go into systems with high reliability this is not something that can be ignored. Everyone in the design and supply chain has a part to play:
Next week, Adrian Evans of IROCtech will present a short webinar on the topic. The agenda is:
The webinar is on Thursday at 11.30am Pacific Time (although I believe Adrian will be presenting from France). I will be the moderator.
To register go here.
IROC is the standard for soft error analysis and prevention. With the introduction of submicron technologies in the semiconductor industry, chips are becoming more vulnerable to radiation induced upsets. IROC Technologies provides chip designers with soft error analysis software, services and expert advisors to improve a chip’s reliability and quality. Exposure of silicon to radiation will happen throughout the lifetime of any IC or device. This vulnerability will grow as development moves to smaller and smaller geometries. IROC proved that the soft errors that cause expensive recalls, time-to-volume slow-down, and product problems in the field can be significantly reduced. The mission of the company’s soft error prevention software and expert advisors is to allow users to increase reliability and quality while significantly lowering the risk of radiation-induced upsets, throughout the lifetime of products under development.
TSMC will be at DAC again this year, of course. The main event, as last year, is the OIP Theater where TSMC’s partners come and present their collaboration stories. Here is the schedule:
Continue reading “TSMC Goes To DAC”
One of the most useful ways to learn about an EDA tool is to talk with other users that have experience with that tool. IC Place and Route tools are complex and yet necessary to implement every SoC designed today, so at DAC in just two weeks you have a chance to hear first-hand from several P&R tool users. To get a better idea about these P&R users and their IC design challenges I talked with Sudhakar Jilla of Mentor Graphics by phone.
Sudhakar Jilla, Mentor Graphics
Continue reading “IC Place and Route Perspective from Users at DAC”
Nvidia designs some of the most powerful graphics chips and systems in the world, so I’m always eager to learn more about their IC design methodology. This week I’ve had the chance to talk with Ting Ku, Director of Engineering at Nvidia about his DAC talkin the Apache booth in exactly two weeks from today. Registration is required for this presentation.
As I have mentioned before, Cliosoft is the biggest little company in EDA with the most talked about products on SemiWiki. At DAC, ClioSoft will introduce integrated SOS design management (DM) solutions providing revision control, design management and multi-site team collaboration for Aglient Technologies’ Advanced Design System (ADS) Software and Mentor Graphics’ Pyxis flow. SOS is now seamlessly integrated into all major analog, RF and custom IC design flows:
In booth #2125 ClioSoft is replacing its popular poker game with slot car racing. As much as I like playing poker, slot car racing brings me back to my childhood so I’m looking forward to it. Maybe next year I can get them to install a massive HO scale train set? My brothers and I spent hours and hours playing with model trains.
Here is what customers are saying about Cliosoft products on SemiWiki:
[LIST=1]
Can you believe this is #50DAC!?!?! I have been to more than half of them (29 to be exact) and will be in Austin for this one too. Funny DAC story, I took my new bride to the 1985 DAC in Las Vegas, my second DAC. We stayed at the MGM and partied quite a bit with the different EDA vendors. I worked for Data General at the time so I had invites to all of the parties. On the way home, as our blood alcohol level went back to 0.00, my wife said to me “So this is what you chose as a career? EDA? Really?” True story. You can ask her about it in Austin because she will be there too.
ClioSoft is the premier developer of hardware configuration management (HCM) solutions. The company’s SOS Design Collaboration platform is built from the ground up to handle the requirements of hardware design flows. The SOS platform provides a sophisticated multi-site development environment that enables global team collaboration, design and IP reuse, and efficient management of design data from concept through tape-out. Custom engineered adaptors seamlessly integrate SOS with leading design flows – Agilent’s Advanced Design System (ADS), Cadence’s Virtuoso® Custom IC, Mentor’s Pyxis Custom IC Design, Synopsys’ Galaxy Custom Designer and Laker™ Custom Design. The Visual Design Diff (VDD) engine enables designers to easily identify changes between two versions of a schematic or layout or the entire design hierarchy below by graphically highlighting the differences directly in the editors.
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My 8 years as an IC circuit designer were at the transistor-level, so if that interests you as well then consider what there is to see from Cadence at DAC this year. IC design technology is changing quickly, so keeping up to date is important for your job security and continual education goals.
Here’s what I would recommend attending at Cadence in Booth #2214: Continue reading “Transistor-Level Update from Cadence at DAC”
