As we get down to smaller and smaller process nodes, the problem of soft errors becomes increasingly important. These soft errors are caused by neutrons from cosmic rays, alpha particles from materials used in manufacture and other sources. For chips that go into systems with high reliability this is not something that can be ignored. Everyone in the design and supply chain has a part to play:
- foundries and packaging for material choice and characterization
- library designers, memory and storage elements
- SoC designers, characterize reliability of design and improve if required
- System architects to define the reliability needed
Next week, Adrian Evans of IROCtech will present a short webinar on the topic. The agenda is:
- Soft Error Rate (SER) trends
- What are the impacts of SER?
- What can be done about it?
- Customer case study
- iROC services and products
The webinar is on Thursday at 11.30am Pacific Time (although I believe Adrian will be presenting from France). I will be the moderator.
To register go here.
IROC is the standard for soft error analysis and prevention. With the introduction of submicron technologies in the semiconductor industry, chips are becoming more vulnerable to radiation induced upsets. IROC Technologies provides chip designers with soft error analysis software, services and expert advisors to improve a chip’s reliability and quality. Exposure of silicon to radiation will happen throughout the lifetime of any IC or device. This vulnerability will grow as development moves to smaller and smaller geometries. IROC proved that the soft errors that cause expensive recalls, time-to-volume slow-down, and product problems in the field can be significantly reduced. The mission of the company’s soft error prevention software and expert advisors is to allow users to increase reliability and quality while significantly lowering the risk of radiation-induced upsets, throughout the lifetime of products under development.Share this post via: