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August 26, 2015August 22, 2024

FD-SOI: GlobalFoundries 22nm Update

FD-SOI: GlobalFoundries 22nm Update
by Paul McLellan on 08-26-2015 at 7:00 am
Categories: FD-SOI, Foundries, GlobalFoundries, STMicroelectronics

As I said yesterday, last week was the GSA Analog/Mixed-Signal working group completely dedicated to FD-SOI. ST went first and had a presentation that was a mixture of an introduction to FD-SOI that I have covered times that are too numerous to mention. Then they did a dive into analog and RF capabilities for FD-SOI that went very deep into two test projects, deeper than I could follow in detail (my PhD is in software not RF design). But the key is in the picture above. The pictures on the right show how back-biasing is actually applied. You apply a positive voltage to the back of the N transistors and a negative one to the back of the P. The graph on the left shows the result. The tiny red line shows how substrate bias works in a bulk process: you can only do a little and it isn’t very effective. The blue line is what you can get with FD-SOI biasing. Actually, since biasing can go to 3V I believe you can do even more. See also FD-SOI: Samsung Opens the Kimono a Little Last up was Jamie Schaeffer of GlobalFoundries. Their introductory slides on the motivation for FD-SOI were largely the same as ST and Samsung. But GF’s process is 22nm, what they call 22FDX. They had 3 reasons for doing 22nm rather than 28nm:

they have a big fab in Dresden that can do 22nm but can’t go to 14nm
22nm doesn’t require double patterning (it is no coincidence that Intel’s first FinFET process was also 22nm)
they can address a bigger market with 22nm than 28nm

They actually have several flavors of the process, to address slightly different markets at the cost of a couple of extra mask steps in most cases. See above for details but the 4 process options are:

ulp: ultra-low power
ull: ulra-low leakage
uhp: ultra-high performance
rfa: integrated RF and analog

The 22FDX body biasing works the same as in 28nm (only more so). With FBB they can get low voltage operation down to 0.4V which is the lowest of any process in existence or that GF knows to be in development. With RBB they can get leakage down to 1pA/um. Those are both impressive numbers. There are also all the advantages in terms of being able to tune gain, linearity, noise immunity and more in analog/RF designs. There are also multiple transistor types which allow you, as you would expect, to get different power/performance points. With FBB and RBB each of these transistors can hit multiple points. See the above diagram for more details. These transistors can all be mixed on the same die. So for an IoT device you can imagine having a little watchdog processor waiting for something to happen: a button press, a timer expires, motion is detected. This can use RBB for the lowest possible leakage. The assumption is that the watchdog does not need much performance, although that can depend on the activity obviously. That can then wake up the comms processor that has integrated RF. Finally a power hungry image processor is awoken using FBB and fast transistors to analyze the scene and zoom on on the area of interest. Then everyone goes back to sleep except the watchdog. The bias gives you a lot of flexibility. There is nothing there yet, but some version of Jamie’s presentation should appear next week on the GSA working groups archive page here. UPDATE: it is now up

August 25, 2015

A Security Idea for EDA / Embedded Design

A Security Idea for EDA / Embedded Design
by Bernard Murphy on 08-25-2015 at 4:00 pm
Categories: EDA

I’m on a mission to find novel ideas for EDA / embedded design tools. One I have been discussing on and off with a DARPA friend for at least a couple of years is how to grade the security of a hardware design or, more comprehensively, the security of an embedded system including hardware and the software running on the hardware.

This feels like something that would be useful to do. After all, in hardware we can grade testability, in hardware and software we can grade test coverage and in ISO26262 there is at least a subjective concept of grading safety risk. Wouldn’t it be nice to know that embedded systems in missiles, personal payment systems, automobiles and medical implants had a similarly objective level of security? Of course these systems have well-defined defenses against known exploits, but intuitively a security metric should not be determined just by defenses against the problems you know but also by also by some measure of security risk in the problems you don’t know.

Security metrics are not very well-developed even in the software space, but there are interesting papers that could be used as a starting point for an embedded security metric. Manadhata and Wing at CMU developed an attack-surface metric for software which considers a static measure of total vulnerability of a system where the attack surface measures through how many directions weaknesses in the system could be attacked. This can be elaborated in several directions, particularly to use “Common Weaknesses and Exposures” documented by the Mitre Corporation as the basic weaknesses around which you build a metric based on accessibility, privilege and so on. An example weakness would be the well-known buffer-overflow problem.

What is appealing about a generalized version of the approach, aside from delivering a metric, is that it depends on a quite finite set of well-known weaknesses (~200 in the Mitre list). Contrast this with the very wide range of possible attack types. What we know about security today focuses almost exclusively on preventing specific classes of attack (stealing a PIN by somehow getting secure access for example) but the total class of possible attacks is almost unbounded. The approach suggested here uses the fact that each attack starts by exploiting one of a relatively small set of weaknesses and is not concerned with the objective or mechanics of the attack.

So to build a metric for the security of an embedded system, we first need a list of Common Weaknesses and Exposures. The Mitre list is a good starting point, and presumably could be enhanced by a list of common weaknesses in hardware. What these should be will require some debate but may not be as difficult as it sounds. Especially worthy of consideration are weaknesses which can enable denial of service or reduction in quality of service; it is often easier to see how these could be accomplished than to see how data could be maliciously injected or stolen from the system. Could you force bridge FIFOs to overflow? Is there a way to cause a cache to repeatedly flush? Can a state-machine be pushed into a deadlock state? Can a privilege be raised on a data transfer from a non-privileged interface IP?

You might argue that if a tool could detect these problems, you would fix them anyway. The same should be true for common software weaknesses and yet they continue to be at the root of almost all software attacks. Apparently the fact that a problem can be detected does not always guarantee it will be corrected. Sometimes this happens through oversight, sometimes because the cost of a fix exceeds the (perceived) value of the fix. But what is an acceptable compromise in one context may not be acceptable in another. A security metric as sketched here would be a way for a prospective customer to assess if an embedded design really meets their security expectations.

Stay tuned for more ideas…

Test Driving Analog/Mixed Signal Design for the Internet of Things

Test Driving Analog/Mixed Signal Design for the Internet of Things
by Beth Martin on 08-25-2015 at 12:00 pm
Categories: EDA, Siemens EDA

The Internet of Things (IoT) is creating urgent demand for a new generation of analog/mixed-signal (AMS) designs, some of which also contain MEMs. To efficiently create the myriad of AMS devices at the edge of the IoT requires a design environment that is affordable and easy to use, but powerful enough to create the widely diverse range of products needed for deployment in the IoT.

Though most of these devices will be inexpensive, there will lots of them – millions and soon billions of form-factors of every description, all created and deployed to gather analog information in the physical world. Wearables may be the media darlings at the moment but in fact examples range from traffic monitoring, smart meters and video surveillance for smart cities, to medical devices that monitor glucose levels, heart rates and mobility and everything in between. And don’t worry, chip designers. These devices will generate a tsunami of analog data that must be digitized and transmitted either to the desktop or to data centers for analysis on phablets, laptops, PCs and servers and systems – all of which contain the more expensive, higher-margin silicon that remains the bread and butter for our industry.

If you’re an AMS designer, you know all about the challenge that comes with creating mostly analog circuitry along with some digital—the so-called ‘Big A/little D’ designs that also can include MEMs functionality. A new generation of affordable, easy-to-use AMS design tools from Mentor Graphics called Tanner AMS IC Design flow is emerging that directly address these challenges, providing a complete flow tailored for the big-A/little-D AMS market for every stage of the design process as well as MEMs. These tools deliver myriad benefits, including increased automation, improved accuracy, lower NRE costs and reduced time to market.

It’s always a tough decision, however, when evaluating and adopting a new set of design tools and capabilities, especially for AMS design. That is why Mentor Graphics has created the Tanner AMS Virtual Lab. Now you can test drive Tanner tools online and experience firsthand how intuitively easy it is to use this powerful, fully integrated and cost-effective AMS design flow. The Virtual Lab covers all aspects of AMS design: schematic capture; mixed-signal simulation or co-simulation; digital synthesis with DFT support; analog place and route; and high-speed, “sign-off ready” timing analysis for tape-out along with MEMs design and layout.

All it takes to access the virtual lab environment is an updated Web browser. There’s no downloading, so no IT department approval is required. Sign up and access to the lab is available for 30 days.

August 25, 2015September 1, 2024

FD-SOI: Samsung Opens the Kimono a Little

FD-SOI: Samsung Opens the Kimono a Little
by Paul McLellan on 08-25-2015 at 7:00 am
Categories: Foundries, Samsung Foundry, STMicroelectronics

Last week there was a meeting of the GSA Analog/Mixed-Signal (AMS) working group. It was completely focused on FD-SOI (I hate that name, especially since FinFET is also fully-depleted. I vote for BoxFETs.) It was a bases loaded meeting with presentations from ST Microelectronics (calling in from France close to midnight), Samsung and GlobalFoundries. That is 3 for 3 of companies that have announced FD-SOI manufacturing.

Here’s the situation. ST got FD-SOI to the commercial manufacturing stage at 28nm. Others, notably IBM, did research in the area (IBM uses partially depleted SOI for its high-end servers, now manufactured by GlobalFoundries, which acquired IBM’s semiconductor business). Samsung announced that they were licensing ST’s process. However, until yesterday, I had not heard much about what the true status was. Then GlobalFoundries announced a 22nm FD-SOI process (actually a family of processes that they market as FDX). The motivation for 22nm was that they wanted a process that was more competitive with 14/16nm FinFET and they wanted to get maximum use out of the existing installed equipment in their Dresden fab. In another wrinkle nothing to do with FD-SOI, GlobalFoundries also licensed Samsung’s 14nm FinFET process.

So on to what Kelvin Low from Samsung said. The main motivation for them to license FD-SOI is that the #1 concern of most customers, and the fastest growing part of the market, is lowest cost per transistor followed closely by low power. People were also concerned with having multiple sources, which had been a problem for ST that Samsung, with its massive manufacturing resources, could help solve. FinFET has a place, obviously, for the leading edge but it delivers high performance but at increased cost, which is the wrong tradeoff for many. FD-SOI involves fewer masks than bulk and about half as many as FinFET (in the front end, the metal stack BEOL is unaffected). Also, the back biasing of FD-SOI is really important. FBB (forward) allows really low voltage operation and RBB (reverse) allows very low leakage standby idle modes. Perfect IoT fodder.

Since this was a mixed-signal working group, Kelvin went into some of the advantages of FD-SOI in the analog RF world. The big advantage of FD-SOI is to be able to use the back-biasing not just to decrease power but add dynamic trimming, gain controlled amplifiers and high gain. Andreia Cathelin of ST had also covered this in her presentation at a level of detail that overwhelmed most of us in the room (certainly me). But the results she had of papers that ST had presented at ISSCC (which I did understand) were undoubtedly impressive. They could do things with FD-SOI that are impossible with bulk (and I think pretty much impossible with FinFET but that is beyond my pay grade).

One thing that I hadn’t realized is that you can run a hybrid process with bulk on some parts of the die (using one extra mask to remove the box) to be able to add ESD structures, BiCMOS options and more. Photomicrograph above.

The current status at Samsung is that wafer level qualification was completed in 2014 and product level reliability in March of this year. PDKs are available. Multiple MPW shuttles are planned (see the graph above for details). The process is currently in its initial ramp, but the base 28nm process of which FD-SOI is a sort of derivative, has alreay run over 2M wafers. The BEOL is completely the same and the FEOL is simpler but still uses the same gate-first HKMG structure.

So what of the future? Things Samsung were not ready to announced (yes, we asked) was what their future process roadmap for FD-SOI would be (22nm, 14nm?). They currently have SRAM, ROM, OTP but are not ready to announce any non-volatile memory option. But you can see some of the directions from the above, Kelvin’s final slide.

There is nothing there yet, but some version of Kelvin’s presentation should appear next week on the GSA working groups archive page here.

And trivia fact of the day. Kimonos are Japanese, as you probably knew. The equivalent in Korea is called a Hanbok.

August 24, 2015June 14, 2019

Testing Ethernet with virtual co-modeling

Testing Ethernet with virtual co-modeling
by Don Dingee on 08-24-2015 at 12:00 pm
Categories: EDA, Siemens EDA

Ethernet is suddenly a hot topic in SoC design again. The biggest news may be this: it’s not just the cloud and enterprise networks. Those are still important applications. The cloud is driving hard for more ports at 25G server and 100G switch speeds according to a recent Dell’Oro Group report. Enterprise networks are driving for more ports at what are becoming intermediate speeds, with Cisco advocating 2.5G and 5G to support existing Cat5 and Cat6 cable. Continue reading “Testing Ethernet with virtual co-modeling”

August 24, 2015

NIWeek: Xilinx Inside

NIWeek: Xilinx Inside
by Paul McLellan on 08-24-2015 at 7:00 am
Categories: FPGA, Xilinx

Being from Britain, NI always means Northern Ireland when I see it. After all the official name of my country is the United Kingdom of Great Britain and Northern Ireland, giving us the same problem as the United States of America, the full name is a mouthful. So we abbreviate the country to UK and call ourselves British or even Brits. But it also stands for National Instruments and every year they have an week-long conference known as NIWeek.

National Instruments are mostly on my radar for a design environment that they have called LabVIEW. As it says on their website:If you can turn it on, drive it or fly it, chances are NI and LabVIEW made it happen.

The product has been around for over 20 years and provides a graphical interface for hooking up everything in the lab and driving the measurement process.

What is NIWeek? The 21st annual NIWeek conference began August 3 in Austin, Texas (where DAC will be for the next two years, by the way), and once again brought together the brightest minds in engineering and science. More than 3,200 innovators representing a wide spectrum of industries, from automotive and telecommunications to robotics and energy, discovered the latest technology to accelerate productivity for software-defined systems in test, measurement, and control.

Most systems in test, measurement and control ship in relatively low volumes, sometimes astoundingly so. When I was doing my PhD I visited HP (presumably now that group will be Agilent if it still exists) and one thing they built was huge analyzers for satellite downlinks. I forget how many they expected to sell but I was surprised how low a number it was (and how much one cost). But back then how many people needed to analyze satellite signals. I bet they sell a lot more with DirectTV, Sky, GPS and more. Low volumes and a reasonable power budget (these are typically not tiny hand-held devices) make it a perfect application for programmable fabrics made by Xilinx, what you probably casually call an FPGA but by the time there are multi-core processors and whole peripheral fabrics, the name is starting to get obsolete. But I suspect Xilinx is fighting a losing battle in trying to get away from it. Like the Association of Computing Machinery just embrace the weirdness of calling your iPhone and its software a machine. It worked for IBM.

Xilinx also has a broad portfolio of different device families at different performance points (and price points). Here is a summary showing the huge range of applications. My favorite, the Phasor Measurement Unit. “Scottie, get that Zynq SoC fired up quickly, the shields are failing.”

There is more detail on most of these applications on Steve Leibson’s Xcell Daily Blog here.

August 23, 2015

My Experience with the Ultra Thin 2015 MacBook

My Experience with the Ultra Thin 2015 MacBook
by Tom Simon on 08-23-2015 at 4:00 pm
Categories: EDA, General, Intel Foundry, Mobile

Before we left for our 5 week trip to Europe I decided that I would need a real laptop computer on the road. I knew it would be a near necessity for booking hotels and making train reservations. Also, I would need to write emails and maybe even pay some online bills. I already have an iPad but really wanted to be able to run all my applications – Excel, Word, Picasa, etc. In looking for the lightest machine that would do this I came across the new MacBook and bought one.

When people see the new MacBook, they think it is a MacBook Air. Apple surprisingly built the new MacBook in a smaller and lighter configuration than the Air. When I first read about it I had to do a double take. The MacBook is 12 inches, in between the 11 and 13-inch Air, but at 2.03 lbs it weighs less and is thinner than the 11 and the 13-inch Air. It uses the new Intel Core M dual core processor. The processor is made on Intel’s 14nm FinFET process and runs at under 5W. For comparison the i7 and i5 typically run at around 15W. The base clock rate is only 1.1 GHz, but it can burst up to 2.4 GHz, putting it in a respectable performance range when needed. It also supports Intel’s Hyperthreading which helps to somewhat further optimize processor utilization.

Unlike the MacBook Air, it comes with a Retina display. The big advantage for me is that I almost always require a second display connected to my laptop to be productive. But with the Retina I can size two ‘full width’ windows side by side and work more efficiently. This means I can really be mobile and productive. Of course this is not a full on production machine like the MacBook Pro, but I really mostly use it for when I am on the road, or maybe when I want to do my writing or check email on my front porch.

The big departure for the MacBook is its choice of a single USB Type-C connector. There is no separate power socket or network port – just the one USB Type-C. (There is a headphone jack too.) The USB Type-C port is used for charging, driving external displays and/or connecting to external USB devices. It supports USB 3.1 at 5 Gb/s. To access the video output via HDMI or to connect traditional USB devices using the more common Type-A connector Apple sells a dongle, but it costs almost $80. Even this does not get you an Ethernet port.

USB Type-C is becoming more common these days. A quick scan on Amazon shows a multitude of devices for it. Surprisingly Apple has left off Thunderbolt. One report attributed this to the power overhead of Thunderbolt. It would grow the main board size and power requirements significantly. Traveling with the MacBook I learned that you can actually charge its battery using a USB battery pack or car USB adapter if needed – a blessing for mobile use. For charging it comes with a 29W wall adapter and a separate standard reversible USB Type-C cable. Those of you who have had to throw away a perfectly good adapter because of a frayed cable will appreciate this.

Apple is betting on 802.11ac for data transfers in and out. Several months ago I bought the Airport Extreme base station with 802.11ac, and it is fast and reliable. So far I have not felt the need to plug a network cable into the MacBook. I have even done a backup of the MacBook to a drive on a networked Mac Mini using the Time Machine app and MacOS Server software.

One caveat is that the MacBook is not up-gradable. The SSD drive and the RAM are soldered in. I have mixed feelings about this. It would be nice to be able to upgrade later. Apple always charges a premium for pre-configured disk and memory, and this leaves buyers with no options. But it comes with 8 GB of RAM so the main choice you need to make besides color is the storage size. I opted for the less expensive 256GB of SSD. This means my large library of pictures stays home, but I have space for lots of Power Point presentations, PDF’s and Word docs. I use DropBox to sync the folders I need so I do not need to think about moving the files I need when I go out.

So what Is the verdict? I’m pretty happy with the MacBook. The SSD means it boots amazingly fast and the overall system performance is excellent. My previous HP laptop has an i7 quad core with a traditional hard rive circa 2011, and for the things I use the MacBook for I have not noticed performance hit. The illuminated keyboard that Mac users love means I can use it in many situations that would have not worked for my old laptop.

Even the track pad works well for me, and I am a die hard mouse user – or at least was. The track pad is pressure sensitive glass with haptic feedback for the click action. This enables more functions in applications and the Finder by pressing harder on the track pad to get a ‘second’ click. In some apps the tack pad allows pressure sensitive drawing.

One of the reasons they made the system non-upgradable was to minimize the main circuit board size. The Core M processor with its integrated Intel HD Graphics 5300 processor have a low profile and small footprint. The bulk of the chassis is filled with batteries. However, this does not buy the user more battery life than say the MacBook Air. This is due to the power hungry Retina display. Without the Core M this machine would have a shorter battery life than the Air.

Older Macs are infamous for getting hot, really hot. The MacBook has a fan-less design, helped by its solid aluminum chassis as a heat sink. It can get warm, but has never been a problem.

For occasional photo editing, writing, posting blogs, web research and spreadsheets the MacBook works excellently. Mind you my home machine has a lot more juice, but I do not really miss it when I’m on the road. The MacBook slides into my backpack pretty easily and it was not hard to schlep across Europe. Overall I am quite happy with the MacBook. I am writing this now on it in a car on I-5 heading up to Mount Shasta, so you can see it is getting a lot of use.

August 23, 2015June 14, 2019

A Complete Simulation Platform for Mobile Systems

A Complete Simulation Platform for Mobile Systems
by Pawan Fangaria on 08-23-2015 at 7:00 am
Categories: Ansys, Inc., EDA, Mobile

If we take an insight into the semiconductor industry, we can easily find that mobile systems are the main drivers of this industry. The Smartphone business has remained at the top since a good number of years. Although the Smartphone sales growth has started showing a sign of stagnation, it is still a main contributor with a solid base in the overall semiconductor revenue. What is the other emerging area? I do not need to tell the obvious, the IoT. Now everything needs connectivity among them, and that’s half baked if not connected with a Smartphone. No wonder smart mobile devices seem to be a business everyone wants to get into. And there are enabling companies providing tools to design the best, robust mobile devices.

What are the key components that go into a modern mobile device? There are many – antenna, battery, different types of sensors, modems, MEMS, wireless charging circuitry, processors, memories, camera, imaging, display, wi-fi, GPS, and so on. The device is complex and has stringent requirements of high performance, low power, low TDP (Thermal Design Power), high reliability under different environments, and so on. Designing such devices or components requires various kinds of simulations to estimate and verify various parameters of a design at different levels including chip, package, electronic board, and even mechanical chassis. It feels great when a single company provides a suite of highly capable simulation tools which can provide a complete integrated solution for simulation of designs for mobile devices.

During 52[SUP]nd[/SUP] DAC, ANSYS along with their customers and partners presented solutions for several design requirements which demonstrate their simulation tools’ calibre in providing the right solution for designing high performance, high reliability mobile devices.

It’s great to hear from SMDH, a company in Brazil that by using RTL driven power integrity flow with PowerArtist for their UHF RFID digital baseband design they could reduce the power consumption by 82%.

Similarly ANSYS has state-of-the-art tools for power delivery optimizations from PCB to package and chip level. They provide an integrated solution for the complete system; system-aware chip as well as chip-aware system solutions. The power noise can be accurately predicted at the PCB level as well as on-chip. A guided methodology can be used to reduce the noise as much as possible.

For mobile devices, battery modeling is an interesting proposition. If a battery can be modelled along with the device where it will be used, nothing like it!

ANSYS Simplorer is a multi-domain, multi-technology simulation system that enables simulation of complex power electronic and electrically controlled systems. ANSYS HFSS has a gold-standard full wave EM field solver. It can automatically generate an efficient and accurate mesh. ANSYS CFD provides fluidic flow analysis capability for designing appropriate structure of a device. To extend the battery life and reliability, the power and thermal budgeting can be done through a set of tools. Power regression can be obtained through the use of PowerArtist and power, noise and reliability signoff can be done by the industry standard RedHawk. There is Sentinel-TI for thermal simulation of 3DIC stacked die.

Power and signal integrity are the key requirements for mobile devices. Noise margin need to be evaluated accurately. ANSYS Q3D provides 3D and 2D EM field simulations for electronic structures. The Q3D and HFSS can be used to evaluate the flow of signals. Sentinel-SSO is used for I/O DDR power, noise and timing analysis. RedHawk can be used to provide accurate IR drop analysis.

A variety of simulation tools on ANSYS simulation platform provide a complete solution for simulation driven design of mobile systems. Different aspects take prime roles at different stages of the system design. For example, at the starting micro-architecture stage power budgeting and reduction takes the prime consideration; at the IP validation stage power delivery and model generation is prime; at the SoC integration stage IR drop, reliability and ESD is critical. The system integration deals with power and signal integrity and thermal analysis at the system level. Then the system design needs to have antenna and wireless power transfer circuits integrated.

ANSYS’ multi-physics simulation platform is quite powerful and caters to a wide range of industry segments. It includes a number of tools for electronic, structural and fluidic simulations involving electrical as well as mechanical aspects of a variety of products for various applications including electrical, electronics, automotive, aerospace, consumer, and more.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

August 23, 2015

A Paradigm Shift in Microelectronic System Design

A Paradigm Shift in Microelectronic System Design
by limingxiu on 08-23-2015 at 7:00 am
Categories: EDA

A Paradigm Shift
The word “paradigm” is defined in the dictionary as “a framework containing the basic assumptions, ways of thinking, and methodology that are commonly accepted by members of a scientific community”. In his influential book “The Structure of Scientific Revolutions” published in 1962, Thomas Kuhn uses the term “a paradigm shift” to indicate a change in the basic assumptions (the paradigms) within the ruling theory of science. Today, this term “paradigm shift” is used widely, both in scientific and non-scientific communities, to describe a profound change in a fundamental model or perception of events.

Ever since the clock concept was introduced into microelectronic system design, it was assumed that all the cycles in a clock pulse train have to be equal in length (a rigorous clock signal). One reason that this form of clock signal has dominated microelectronic system design for a long time is that, in the past, the requirement for IC clocking was mostly straightforward. A clock signal with a fixed rate was sufficient for most systems. However, the complexity of future systems changes the game. Low power operation, low electromagnetic radiation, synchronization among networked devices (e.g. Internet of Things), complex data communication schemes, etc., all require a clock signal that is flexible.

Another reason behind the dominance of this style of rigorous clock is that time, which shows its existence and its flow indirectly through the use of a clock pulse train, is not a physical entity that can be controlled and observed directly. Thus, creating flexible clock is an inherently difficult task. It demands effort beyond simply playing with various techniques at circuit level. Philosophically it requires an adjustment, at fundamental level, in our thinking about the way of clocking microelectronic system. The “anomaly” in this case is a new perspective on the concept of clock frequency. In this line of argument, the materials presented in this book induce a paradigm shift in the field of microelectronic system design.

Clock is an enabler for system level innovation
Viewing from high level, there are four fundamental technologies supporting the entire IC design business: processor technology, memory technology, analog/RF technology and clock technology. In the past several decades, a tremendous amount of effort has been spent on the development of the first three technologies. Clock technology falls behind in this race. One of the key reasons for this is that clock technology deals with a special entity: time. Neither is it directly observable nor is it directly controllable. The circuit designer can only play with it indirectly, through voltage and/or current. This lag, however, provides us an opportunity to make significant progress. It is a battleground for new ideas. It is a potential birthplace for great inventions. It is one of the enablers for system level innovation.

What is new on clock? flexibility versus spectrum purity
When the term “flexible clock” is used, it refers to a clock signal: 1) whose frequency can be arbitrarily set; and 2) whose frequency can be changed quickly. Preferably, these two features shall be achieved simultaneously and be available to clock user at a reasonable cost. A rigorous clock has the characteristic of high spectrum purity, which is beneficial to certain applications. There are, however, many more applications where spectrum purity is not of high concern. Instead, a clock signal possessing the capability of small frequency granularity and fast frequency switching is more useful. Therefore, there is a crucial trade-off to be made when an IC design problem is investigated. In the past, clock of high spectrum purity was the undeniable winner. However, for future microelectronic system design, this is not necessarily always the case.

“Jittery” clock is not necessarily a bad thing
The essence of a clock pulse train is to create a series of “moments in flow-of-time” by utilizing the mechanism of “voltage-level-crossing-a-threshold”. The resulting moments are used as the reference points for other events happening inside the microelectronic system. Therefore, the requirement on those moments is that their location-in-time must be predictable and precise. Jitter is a parameter measuring this quality. Thus, jittery clock is undesirable since it reduces the effectiveness of the clock in coordinating other events. However, jitter is not without any use. An obvious example of its applicability is that jitter in a clock signal can help reduce its electromagnetic radiation since it spreads the clock energy. Another not-so-obvious, and more valuable, use of “jittery” clock is to trade the irregularity-in-moment with the flexibility. The flexibility associated with a clock signal refers to its capability of fine frequency resolution and fast frequency switching. When use with care of this irregularity-in-moment, a clock signal can be made flexible by intentionally introducing “controlled jitter” into it. This capability is important for certain applications. Indeed, it outweighs the requirement on clock’s spectrum purity in such applications. Hence, jittery clock is not necessarily a bad thing.

The power of idea
Many times in human history, the power of an idea has changed the landscape of our civilization. Such ideas include liberty, romanticism, Marxism, Zionism, among others. Each of these great ideas leaded to a profound movement that changed the way we live. In science and technology, the latest example of such an idea would be Einstein’s theory of relativity. It links the space and time together, resulting in a thing called space-time. This breakthrough idea, which was regarded as a ridiculous one by most people when it made its debut, is proven to be one of the greatest in human history. This idea is an “anomaly” that later leads to a great paradigm shift in science.

In book “Nanometer Frequency Synthesis beyond Phase Locked Loop”, a new perspective on clock frequency was introduced. While the materials presented in that book focuses on building the circuit at component level, this book will answer the question of how to use it in upper level to create better systems. This book is the continuation in this route of new microelectronic system design methodology. Quoted from Steve Job: think different.

From Frequency to Time-Average-Frequency: A Paradigm Shift in the Design of Electronic System (IEEE Press Series…

August 21, 2015

Four Things a New Semiconductor Technology Must Have to be Disruptive

Four Things a New Semiconductor Technology Must Have to be Disruptive
by Alex Lidow on 08-21-2015 at 12:00 pm
Categories: EDA

This post discusses attributes of gallium nitride (#GaN) that make it a disruptive technology and identifies the four factors required for GaN technology to displace silicon as the technology of choice.

Displacing the Silicon with GaN
38 years ago, when I first entered the semiconductor business as a freshly minted Stanford Ph.D., my first project was to develop a transistor that would be better than the aging silicon-based bipolar transistor that was invented in 1947 at Bell Labs by Brattain, Bardeen, and Shockley (They won the 1956 Nobel Prize for this development). My colleague, Tom Herman, and I set out to disrupt this 30 year old technology by using the latest techniques developed for integrated circuits. From this effort, and an incredible team of contributors, came the power MOSFET (We branded ours the HEXFET). It was a disruptive technology, and it did largely displace the bipolar transistor over a period of about 15 years. The dynamics of this transition taught us that there were four key factors controlling the adoption rate of a new semiconductor technology:

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Does it enable significant new applications?

Is it easy to use?

Is it VERY cost effective to the user?

Is it reliable?

Let’s now address each of these questions individually for the next generation of technology – GaN compared with silicon in the field of power conversion.

Does it enable significant new applications?
Some examples of large new applications that are made possible primarily because of the higher switching speed of GaN transistors include:

Envelope Tracking: This is a power supply technique that can double the energy efficiency of RF power amplifiers used to transmit all of our voice and data through satellites, base stations, and cell phones. Envelope tracking is accomplished by tracking the power demand precisely and providing the power to exactly fit the amplifiers signal modulation needs. Today, RF power amplifiers operate at a fixed power level delivering maximum power whether or not the transmitter needs it. Excitingly enough, GaN transistors are the first transistors capable of tracking power demands at the high data transmission rates used in 4G LTE network base stations!
Wireless Power: Cut the cord! Wireless power transfer enables cell phone, game controllers, laptop computers, tablets, and even electric vehicles to re-charge without being plugged in. A high frequency standard (6.78 MHz) for power transmission is currently being adopted by an industry consortium(A4WP). Silicon power devices (power MOSFETs) do not perform well at speeds this fast, whereas GaN transistors and integrated circuits offer an alternative that switches fast enough to be ideal.
LiDAR (Light Distancing And Ranging): LiDAR uses pulsed lasers to rapidly create a three dimensional image of a surrounding area. This technique is widely used for geographic mapping functions and is technology driving (so to speak) “driverless” cars. The higher switching speed of GaN transistors drive superior resolution and response time that enable LiDAR applications beyond the mapping functions to applications such as augmented reality and fully autonomous vehicles.

Is it easy to use?
At EPC we designed our GaN transistors (eGaN FETs) to be very similar in behavior to the aging power MOSFETs, and therefore power systems engineers can use their design experience with minimal additional training. To assist design engineers up the learning curve, EPC has established itself as the leader in educating the industry about gallium nitride devices and their applications. As a matter of fact, in addition to publishing over 100 articles and presentations, in 2011 EPC published the industry’s first GaN transistor textbook (in English and Chinese) – GaN Transistors for Efficient Power Conversion. The second edition was published in 2015 by J. Wiley and is available through Amazon as well as textbook retailers. EPC is working with more than 60 universities around the world in order to lay the groundwork for the next generation of highly skilled power system designers trained in getting the most out of GaN technology

Is it VERY cost effective?
GaN transistors and integrated circuits from EPC are produced using processes similar to silicon power MOSFETs, and actually have many fewer processing steps than MOSFETs. In addition, GaN transistors do not require the costly packaging needed to protect their silicon predecessors. This packaging advantage alone can cut the cost of manufacture in half and, combined with high manufacturing yields, has resulted in the cost of a GaN transistor from EPC to belower in cost than a comparable (but lower performance) silicon power MOSFET. Today the designer does not even need to take advantage of the higher performance of GaN to realize cost savings in the system!

Is it reliable?
To date, tens of millions of hours of stress testing from several manufacturers, and tens of billions of device hours in demanding applications such as truck headlamps, drones, and base stations suggest this technology is capable of performing at acceptable levels of reliability in commercial applications today.

Summary
Thus, fast switching speed, small size, competitive cost, and high reliability give the GaN transistor the attributes needed to displace the silicon MOSFET in power conversion applications. Similar analysis show that soon the same will be true for analog integrated circuits. Perhaps in 3-5 years the same will be true for digital integrated circuits. GaN is a relatively new technology and has just begun its journey up the learning curve!

Also read: GaN Technology for the Connected Car